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Implementing CRYSTALS-Dilithium Signature Scheme on FPGAs

Published: 17 August 2021 Publication History

Abstract

In July 2020, the lattice-based CRYSTALS-Dilithium digital signature scheme has been chosen as one of the three third-round finalists in the post-quantum cryptography standardization process by the National Institute of Standards and Technology (NIST). In this work, we present the first Very High Speed Integrated Circuit Hardware Description Language (VHDL) implementation of the CRYSTALS-Dilithium signature scheme for Field-Programmable Gate Arrays (FPGAs). Due to our parallelization-based design requiring only low numbers of cycles, running at high frequency and using reasonable amount of hardware resources on FPGA, our implementation is able to sign 15832 messages per second and verify 10524 signatures per second. In particular, the signing algorithm requires 68461 Look-Up Tables (LUTs), 86295 Flip-Flops (FFs), and the verification algorithm takes 61738 LUTs and 34963 FFs on Virtex 7 UltraScale+ FPGAs. In this article, experimental results for each Dilithium security level are provided and our VHDL-based implementation is compared with related High-Level Synthesis (HLS)-based implementations. Our solution is ca 114 times faster (in the signing algorithm) and requires less hardware resources.

References

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Cited By

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  • (2025)PUF-Dilithium: Design of a PUF-Based Dilithium Architecture Benchmarked on ARM ProcessorsACM Transactions on Embedded Computing Systems10.1145/3715328Online publication date: 25-Jan-2025
  • (2024)Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-DilithiumACM Transactions on Reconfigurable Technology and Systems10.1145/367517217:3(1-26)Online publication date: 30-Sep-2024
  • (2024)A Low-Latency Polynomial Multiplier Accelerator for CRYSTALS-Dilithium Digital SignatureProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658794(258-262)Online publication date: 12-Jun-2024
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cover image ACM Other conferences
ARES '21: Proceedings of the 16th International Conference on Availability, Reliability and Security
August 2021
1447 pages
ISBN:9781450390514
DOI:10.1145/3465481
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 August 2021

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Author Tags

  1. Digital signatures
  2. FPGA
  3. Lattice-based cryptography
  4. Number-theoretic transform
  5. Optimization.
  6. Parallelization
  7. Post-quantum cryptography
  8. VHDL implementation

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ARES 2021

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Overall Acceptance Rate 228 of 451 submissions, 51%

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Cited By

View all
  • (2025)PUF-Dilithium: Design of a PUF-Based Dilithium Architecture Benchmarked on ARM ProcessorsACM Transactions on Embedded Computing Systems10.1145/3715328Online publication date: 25-Jan-2025
  • (2024)Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-DilithiumACM Transactions on Reconfigurable Technology and Systems10.1145/367517217:3(1-26)Online publication date: 30-Sep-2024
  • (2024)A Low-Latency Polynomial Multiplier Accelerator for CRYSTALS-Dilithium Digital SignatureProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658794(258-262)Online publication date: 12-Jun-2024
  • (2024)REPQC: Reverse Engineering and Backdooring Hardware Accelerators for Post-quantum CryptographyProceedings of the 19th ACM Asia Conference on Computer and Communications Security10.1145/3634737.3657016(533-547)Online publication date: 1-Jul-2024
  • (2024)Post-Quantum Signatures on RISC-V with Hardware AccelerationACM Transactions on Embedded Computing Systems10.1145/357909223:2(1-23)Online publication date: 27-Mar-2024
  • (2024)Hardware Circuits and Systems Design for Post-Quantum Cryptography—A Tutorial BriefIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2024.335783671:3(1670-1676)Online publication date: Mar-2024
  • (2024)A High Speed Post-Quantum Crypto-Processor for Crystals-DilithiumIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.330441671:1(435-439)Online publication date: Jan-2024
  • (2024)Post-Quantum SecureSensor Networks: Combining Ascon and SPHINCS+2024 IEEE 4th International Conference on Electronic Communications, Internet of Things and Big Data (ICEIB)10.1109/ICEIB61477.2024.10602653(139-144)Online publication date: 19-Apr-2024
  • (2024)An Efficient Hardware/Software Co-Design for FALCON on Low-End Embedded SystemsIEEE Access10.1109/ACCESS.2024.338748912(57947-57958)Online publication date: 2024
  • (2024)Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature StandardIEEE Access10.1109/ACCESS.2024.337047012(32395-32407)Online publication date: 2024
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