research-article

A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process

Authors:

Saibal MukhopadhyayAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 18, Issue 1

Article No.: 20, Pages 1 - 20

https://doi.org/10.1145/3466681

Published: 03 November 2021 Publication History

Abstract

We present a ReRAM memory compiler for monolithic 3D (M3D) integrated circuits (IC). We develop ReRAM architectures for M3D ICs using 1T-1R bit cells and single and multiple tiers of transistors for access and peripheral circuits. The compiler includes an automated flow for generation of subarrays of different dimensions and larger arrays of a target capacity by integrating multiple subarrays. The compiler is demonstrated using an M3D process design kit (PDK) based on a Carbon Nanotube Transistor technology. The PDK includes multiple layers of transistors and back-end-of-the-line integrated ReRAM. Simulations show the compiled ReRAM macros with multiple tiers of transistors reduces footprint and improves performance over the macros with single-tier transistors. The compiler creates layout views that are exported into library exchange format or graphic data system for full-array assembly and schematic/symbol views to extract per-bit read/write energy and read latency. Comparison of the proposed M3D subarray architectures with baseline 2D subarrays, generated with a custom-designed set of bit cells and peripherals, demonstrate up to 48% area reduction and 13% latency improvement.

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Cited By

Chen SWu CCai YGuan YCheng Y(2024)3D SRAM Design & Optimization with Open Source Memory Compiler2024 International 3D Systems Integration Conference (3DIC)10.1109/3DIC63395.2024.10830085(1-5)Online publication date: 25-Sep-2024
https://doi.org/10.1109/3DIC63395.2024.10830085
Siddique AHoque K(2023)Moving Target Defense Through Approximation for Low-Power Neuromorphic Edge IntelligenceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332709343:3(728-741)Online publication date: 25-Oct-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3327093

Index Terms

A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process
1. Hardware
  1. Emerging technologies

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Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 18, Issue 1

January 2022

497 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/3483339

Editor:
Ramesh Karri
Polytechnic Institute of New York University, USA

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Copyright © 2021 Association for Computing Machinery.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 03 November 2021

Accepted: 01 May 2021

Revised: 01 February 2021

Received: 01 September 2020

Published in JETC Volume 18, Issue 1

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Cited By

Chen SWu CCai YGuan YCheng Y(2024)3D SRAM Design & Optimization with Open Source Memory Compiler2024 International 3D Systems Integration Conference (3DIC)10.1109/3DIC63395.2024.10830085(1-5)Online publication date: 25-Sep-2024
https://doi.org/10.1109/3DIC63395.2024.10830085
Siddique AHoque K(2023)Moving Target Defense Through Approximation for Low-Power Neuromorphic Edge IntelligenceIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332709343:3(728-741)Online publication date: 25-Oct-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3327093

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