ABSTRACT
The electric locomotives of electrified railway are non-linear loads, injecting harmonics into the power system and deteriorating the power quality. In order to assess the impact of harmonics on power quality and provide the basis for harmonic suppression, a harmonic model combining with polynomial model and probability model is proposed in this paper. First, the paper derives the formula of current harmonics, illustrating that active power and grid-side voltage are the key factors affecting harmonics. Then, based on the measured data of CRH6 EMU, the influence of active power, reactive power, power factor, and grid-side voltage on harmonics in traction and regenerative braking conditions is investigated respectively. After that, a harmonic model combining polynomial model and probability model is proposed. Finally, the model proves to be effective by measured data.
- H. Hu, Y. Shao, L. Tang, Z. He, and S. Gao. “Overview of harmonic and resonance in railway electrification systems,” IEEE Transactions on Industry Applications, vol. 54, pp. 5227-5245, 2018.Google ScholarCross Ref
- H. Hu, Z. He, X. Li, K. Wang, and S. Gao. “Power-quality impact assessment for high-speed railway associated with High-Speed trains using train timetable—Part I: Methodology and Modelling,” IEEE Transactions on Power Delivery, vol. 31, pp. 693-703, 2016.Google ScholarCross Ref
- K. Wang, H. Hu, J. Chen, J. Zhu, X. Zhong, and Z. He. “System-Level dynamic energy consumption evaluation for High-Speed Railway.,” IEEE Transactions on Transportation Electrification, vol. 5, pp. 745-757, 2019.Google ScholarCross Ref
- S. Papathanassiou, M. Papadopoulos. “Harmonic analysis in a power system with wind generation,” IEEE Transactions on Power Delivery, vol. 21, pp. 2006-2016, 2006.Google ScholarCross Ref
- E. Thunberg, L. Soder. “A Norton approach to distribution network modelling for harmonic studies,” IEEE Transactions on Power Delivery, vol. 14, pp. 272-277, 1999.Google ScholarCross Ref
- J. Arrillaga, A. Medina, M. L. V. Lisboa, M. A. Cavia, and P. Sanchez. “The harmonic domain. a frame of reference for power system harmonic analysis,” IEEE Transactions on Power Systems, vol. 10, pp. 433-440, 1995.Google ScholarCross Ref
- M. Fauri. “Harmonic modelling of non-linear load by means of crossed frequency admittance matrix,” IEEE Transactions on Power Systems, vol. 12, pp. 1632-1638, 1997.Google ScholarCross Ref
- Y. Baghzouz, O. T. Tan. “Probabilistic modelling of power system harmonics,” IEEE Transactions on Industry Applications, vol. 23, pp. 173-180, 1987.Google ScholarCross Ref
- J. Zhu, H. Hu. Z. He., X. Guo and W. Pan. “A power-quality monitoring and assessment system for high-speed railways based on train-network-data center integration,” Railway Engineering Science, vol. 29, pp. 30-41, 2021.Google ScholarCross Ref
- X. Ge, Y. Liu. “A dynamic parameter model of harmonic source networks,” IEEE Transactions on Power Delivery, vol. 35, pp. 1093-1101, 2020.Google ScholarCross Ref
- J. Jiao, Z. Zhang. S. Liu, F. Lin, and Z. Yang.“Harmonics influence factors analysis for four-quadrant converters of High-Speed train,” The 2015 International Conference on Electrical and Information Technologies for Rail Transportation. Berlin, Heidelberg. pp. 277-288, 2015.Google Scholar
Recommendations
A CMOS even harmonic mixer with current reuse for low power applications
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designThis paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs current reuse and double frequency circuits in the RF input stage and LO stage, respectively, to improve its linearity and isolation. In addition, the ...
Equalization and pre-emphasis based LVDS transceiver
This work presents an area-efficient, low-power, high data rate low voltage differential signal (LVDS) transmitter and receiver with signal quality enhancing techniques. The proposed common mode feedback scheme significantly reduces the size of the LVDS ...
A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock
This paper presents a wide frequency range CDR circuit for second generation AiPi+ intra-panel interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with conventional AiPi+. The DLL-based CDR architecture is ...
Comments