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Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision

Published: 13 September 2021 Publication History

Abstract

Low-density parity-check (LDPC) codes have been widely adopted in NAND flash in recent years to enhance data reliability. There are two types of decoding, hard-decision and soft-decision decoding. However, for the two types, their error correction capability degrades due to inaccurate log-likelihood ratio (LLR). To improve the LLR accuracy of LDPC decoding, this article proposes LLR optimization schemes, which can be utilized for both hard-decision and soft-decision decoding. First, we build a threshold voltage distribution model for 3D floating gate (FG) triple level cell (TLC) NAND flash. Then, by exploiting the model, we introduce a scheme to quantize LLR during hard-decision and soft-decision decoding. And by amplifying a portion of small LLRs, which is essential in the layer min-sum decoder, more precise LLR can be obtained. For hard-decision decoding, the proposed new modes can significantly improve the decoder’s error correction capability compared with traditional solutions. Soft-decision decoding starts when hard-decision decoding fails. For this part, we study the influence of the reference voltage arrangement of LLR calculation and apply the quantization scheme. The simulation shows that the proposed approach can reduce frame error rate (FER) for several orders of magnitude.

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  • (2024)Characterizing and Optimizing LDPC Performance on 3D NAND Flash MemoriesACM Transactions on Architecture and Code Optimization10.1145/366347821:3(1-26)Online publication date: 3-May-2024
  • (2024)Modeling Retention Errors of 3D NAND Flash for Optimizing Data PlacementACM Transactions on Design Automation of Electronic Systems10.1145/365910129:4(1-24)Online publication date: 21-Jun-2024
  • (2024)LLD: Lightweight Latency Decrease Scheme of LDPC Hard Decision Decoding for 3-D TLC NAND Flash MemoryIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.343878971:10(4611-4623)Online publication date: Oct-2024
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      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 27, Issue 1
      January 2022
      230 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/3483335
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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      Publication History

      Published: 13 September 2021
      Accepted: 01 June 2021
      Revised: 01 May 2021
      Received: 01 October 2020
      Published in TODAES Volume 27, Issue 1

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      Author Tags

      1. LLR
      2. LDPC
      3. TLC NAND flash
      4. threshold voltage distribution
      5. reference voltage

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      • Research-article
      • Refereed

      Funding Sources

      • Key Area Research and Development Program of Guangdong Province
      • NSFC
      • National Key Research and Development Program of China
      • 111 Project
      • China Postdoctoral Science Foundation
      • Postdoctoral Innovative Talents Support Program
      • Excellent Projects for Postdoctoral Science and Technology Activities in Hubei Province
      • Key Project of Shandong Wisdom Joint Fund

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      Cited By

      View all
      • (2024)Characterizing and Optimizing LDPC Performance on 3D NAND Flash MemoriesACM Transactions on Architecture and Code Optimization10.1145/366347821:3(1-26)Online publication date: 3-May-2024
      • (2024)Modeling Retention Errors of 3D NAND Flash for Optimizing Data PlacementACM Transactions on Design Automation of Electronic Systems10.1145/365910129:4(1-24)Online publication date: 21-Jun-2024
      • (2024)LLD: Lightweight Latency Decrease Scheme of LDPC Hard Decision Decoding for 3-D TLC NAND Flash MemoryIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.343878971:10(4611-4623)Online publication date: Oct-2024
      • (2024)LVLDPC: Intra-Layer Variation Aware LDPC Coding for 3D TLC NAND Flash Memory2024 IEEE 42nd International Conference on Computer Design (ICCD)10.1109/ICCD63220.2024.00080(483-486)Online publication date: 18-Nov-2024

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