Lanlan Cui
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Abstract
Low-density parity-check (LDPC) codes have been widely adopted in NAND flash in recent years to enhance data reliability. There are two types of decoding, hard-decision and soft-decision decoding. However, for the two types, their error correction capability degrades due to inaccurate log-likelihood ratio (LLR). To improve the LLR accuracy of LDPC decoding, this article proposes LLR optimization schemes, which can be utilized for both hard-decision and soft-decision decoding. First, we build a threshold voltage distribution model for 3D floating gate (FG) triple level cell (TLC) NAND flash. Then, by exploiting the model, we introduce a scheme to quantize LLR during hard-decision and soft-decision decoding. And by amplifying a portion of small LLRs, which is essential in the layer min-sum decoder, more precise LLR can be obtained. For hard-decision decoding, the proposed new modes can significantly improve the decoder’s error correction capability compared with traditional solutions. Soft-decision decoding starts when hard-decision decoding fails. For this part, we study the influence of the reference voltage arrangement of LLR calculation and apply the quantization scheme. The simulation shows that the proposed approach can reduce frame error rate (FER) for several orders of magnitude.
- Lalit Bahl, John Cocke, Frederick Jelinek, and Josef Raviv. 1974. Optimal decoding of linear codes for minimizing symbol error rate (corresp.). IEEE Transactions on Information Theory 20, 2 (1974), 284–287. Google Scholar
Digital Library
- Raj Chandra Bose and Dwijendra K. Ray-Chaudhuri. 1960. On a class of error correcting binary group codes. Information and Control 3, 1 (1960), 68–79.Google ScholarCross Ref
- Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, and Onur Mutlu. 2017. Error characterization, mitigation, and recovery in flash-memory-based solid-state drives. Proc. IEEE 105, 9 (2017), 1666–1704.Google ScholarCross Ref
- Yu Cai, Erich F. Haratsch, Onur Mutlu, and Ken Mai. 2013. Threshold voltage distribution in MLC NAND flash memory: Characterization, analysis, and modeling. In 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1285–1290. Google ScholarDigital Library
- Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, and Onur Mutlu. 2015. Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. In 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA). 551–563.Google ScholarCross Ref
- Jinghu Chen, Ajay Dholakia, Evangelos Eleftheriou, Marc P. C. Fossorier, and Xiao-Yu Hu. 2005. Reduced-complexity decoding of LDPC codes. IEEE Transactions on Communications 53, 8 (2005), 1288–1299.Google ScholarCross Ref
- Shih-Liang Chen, Bo-Ru Ke, Jian-Nan Chen, and Chih-Tsun Huang. 2011. Reliability analysis and improvement for multi-level non-volatile memories with soft information. In 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC). IEEE, 753–758. Google ScholarDigital Library
- Yoshiaki Deguchi, Shun Suzuki, and Ken Takeuchi. 2018. Write and read frequency-based word-line batch VTH modulation for 2-D and 3-D-TLC NAND flash memories. IEEE Journal of Solid-State Circuits99 (2018), 1–10.Google Scholar
- Guiqiang Dong, Ningde Xie, and Tong Zhang. 2010. On the use of soft-decision error-correction codes in NAND flash memory. IEEE Transactions on Circuits and Systems I: Regular Papers 58, 2 (2010), 429–439.Google ScholarCross Ref
- G. Forney. 1965. On decoding BCH codes. IEEE Transactions on Information Theory 11, 4 (1965), 549–557. Google ScholarDigital Library
- Marc P. C. Fossorier, Miodrag Mihaljevic, and Hideki Imai. 1999. Reduced complexity iterative decoding of low-density parity check codes based on belief propagation. IEEE Transactions on Communications 47, 5 (1999), 673–680.Google ScholarCross Ref
- Robert Gallager. 1962. Low-density parity-check codes. IRE Transactions on Information Theory 8, 1 (1962), 21–28.Google ScholarCross Ref
- Guangjun Ge and Liuguo Yin. 2017. LDPC coding scheme for improving the reliability of multi-level-cell NAND flash memory in radiation environments. China Communications 14, 8 (2017), 10–21.Google ScholarCross Ref
- Frédéric Guilloud, Emmanuel Boutillon, and Jean-Luc Danger. 2003. -min decoding algorithm of regular and irregular LDPC codes. In 3rd International Symposium on Turbo Codes and Related Topics. 451–454.Google Scholar
- Kin-Chu Ho, Po-Chao Fang, Hsiang-Pang Li, Cheng-Yuan Michael Wang, and Hsie-Chia Chang. 2013. A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine. In 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers. IEEE, 222–223.Google Scholar
- Hoda Aghaei Khouzani and Chengmo Yang. 2016. Towards a scalable and write-free multi-version checkpointing scheme in solid state drives. In 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN). IEEE, 37–48.Google ScholarCross Ref
- Jonghong Kim and Wonyong Sung. 2013. Rate-0.96 LDPC decoding VLSI for soft-decision error correction of NAND flash memory. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, 5 (2013), 1004–1015.Google Scholar
- Taehyung Kim, Gyuyeol Kong, Xi Weiya, and Sooyong Choi. 2013. Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory. IEEE Transactions on Magnetics 49, 6 (2013), 2569–2573.Google ScholarCross Ref
- Khoa Le and Fakhreddine Ghaffari. 2018. On the use of hard-decision LDPC decoders on MLC NAND flash memory. In 2018 15th International Multi-Conference on Systems, Signals & Devices (SSD). IEEE, 1453–1458.Google ScholarCross Ref
- Bertrand Le Gal and Christophe Jego. 2015. High-throughput multi-core LDPC decoders based on x86 processor. IEEE Transactions on Parallel and Distributed Systems 27, 5 (2015), 1373–1386. Google ScholarDigital Library
- Huanlin Li, Yanyan Cao, and Jeffrey C. Dill. 2010. Analysis of error-prone patterns for LDPC codes under belief propagation decoding. In 2010 Military Communications Conference (2010 MILCOM). IEEE, 2056–2061.Google Scholar
- Qiao Li, Liang Shi, Chun Jason Xue, Qingfeng Zhuge, and Edwin H-M Sha. 2017. Improving LDPC performance via asymmetric sensing level placement on flash memory. In 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 560–565.Google ScholarCross Ref
- Yixin Luo. 2018. Architectural techniques for improving NAND flash memory reliability. arXiv preprint arXiv:1808.04016 (2018).Google Scholar
- Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, and Onur Mutlu. 2016. Enabling accurate and practical online flash channel modeling for modern MLC NAND flash memory. IEEE Journal on Selected Areas in Communications 34, 9 (2016), 2294–2311. Google ScholarDigital Library
- Mohammad M. Mansour and Naresh R. Shanbhag. 2002. Low-power VLSI decoder architectures for LDPC codes. In International Symposium on Low Power Electronics and Design. IEEE, 284–289. Google ScholarDigital Library
- Thomas Parnell, Nikolaos Papandreou, Thomas Mittelholzer, and Haralampos Pozidis. 2014. Modelling of the threshold voltage distributions of sub-20nm NAND flash memory. In 2014 IEEE Global Communications Conference. IEEE, 2351–2356.Google ScholarCross Ref
- Santini Paolo, Battaglioni Massimo, Baldi Marco, and Chiaraluce Franco. 2019. Hard-decision iterative decoding of LDPC codes with bounded error rate. In 2019 IEEE International Conference on Communications (ICC). IEEE, 1–6.Google Scholar
- C. van Ingen and J. Gray. 2005. Empirical Measurements of Disk Failure rates and Error Rates. Technical Report. MSR-TR-2005.Google Scholar
- Jiadong Wang, Thomas Courtade, Hari Shankar, and Richard D. Wesel. 2011. Soft information for LDPC decoding in flash: Mutual-information optimized quantization. In 2011 IEEE Global Telecommunications Conference (GLOBECOM 2011). IEEE, 1–6.Google Scholar
- Jiadong Wang, Kasra Vakilinia, Tsung-Yi Chen, Thomas Courtade, Guiqiang Dong, Tong Zhang, Hari Shankar, and Richard Wesel. 2014. Enhanced precision through multiple reads for LDPC decoding in flash memories. IEEE Journal on Selected Areas in Communications 32, 5 (2014), 880–891.Google ScholarCross Ref
- Fei Wu, Meng Zhang, Yajuan Du, Weihua Liu, Zuo Lu, Jiguang Wan, Zhihu Tan, and Changsheng Xie. 2020. Using error modes aware LDPC to improve decoding performance of 3-D TLC NAND flash. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, 4 (2020), 909–921.Google ScholarCross Ref
- Yunxiang Wu, Yu Cai, and Erich F. Haratsch. 2017. Fixed point conversion of LLR values based on correlation. US Patent 9,582,361.Google Scholar
- Ningde Xie, Guiqiang Dong, and Tong Zhang. 2010. Applying transparent lossless data compression to improve the feasibility of using advanced error correction codes in solid-state drives. In 2010 IEEE Workshop on Signal Processing Systems. IEEE, 31–35.Google ScholarCross Ref
- Qin Xiong, Fei Wu, Zhonghai Lu, Yue Zhu, You Zhou, Yibing Chu, Changsheng Xie, and Ping Huang. 2017. Characterizing 3D floating gate NAND flash. In 2017 ACM SIGMETRICS/International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS 2017) (University of Illinois Urbana-ChampaignUrbana-Champaign, IL, 5 June 2017 through 9 June 2017). Association for Computing Machinery (ACM), 31–32. Google ScholarDigital Library
- Cristian Zambelli, Giuseppe Cancelliere, Fabrizio Riguzzi, Evelina Lamma, Piero Olivo, Alessia Marelli, and Rino Micheloni. 2017. Characterization of TLC 3D-NAND flash endurance through machine learning for LDPC code rate optimization. In 2017 IEEE International Memory Workshop (IMW). IEEE, 1–4.Google ScholarCross Ref
- Meng Zhang, Fei Wu, Yajuan Du, Weihua Liu, and Changsheng Xie. 2019. Pair-bit errors aware LDPC decoding in MLC NAND flash memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, 12 (2019), 2312–2320.Google ScholarDigital Library
- Meng Zhang, Fei Wu, Xubin He, Ping Huang, Shunzhuo Wang, and Changsheng Xie. 2016. REAL: A retention error aware LDPC decoding scheme to improve NAND flash read performance. In 2016 32nd Symposium on Mass Storage Systems and Technologies (MSST). IEEE, 1–13.Google ScholarCross Ref
Index Terms
- Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision
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