ABSTRACT
An efficient parallelized Huffman decoding PE is proposed in this paper. The classic Huffman decoding algorithm is optimized first in parallel processing and then four hardware modules are designed based on that. The proposed PE can decode different numbers of streams with various compression ratios. The hardware architecture is fully verified at RTL level and synthesized with GF 12nm technology lib. The simulation shows a better decoding performance especially with wide data width and high compression ratio settings.
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