Kazi Asifuzzaman
Rommel Sánchez Verdejo
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Abstract
It is questionable whether DRAM will continue to scale and will meet the needs of next-generation systems. Therefore, significant effort is invested in research and development of novel memory technologies. One of the candidates for next-generation memory is Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). STT-MRAM is an emerging non-volatile memory with a lot of potential that could be exploited for various requirements of different computing systems. Being a novel technology, STT-MRAM devices are already approaching DRAM in terms of capacity, frequency, and device size. Although STT-MRAM technology got significant attention of various major memory manufacturers, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing and current parameters of this novel technology, which are required to perform a reliable main memory simulation on performance and power estimation. This study demonstrates an approach to perform a cycle accurate simulation of STT-MRAM main memory, being the first to release detailed timing and current parameters of this technology from academia—essentially enabling researchers to conduct reliable system-level simulation of STT-MRAM using widely accepted existing simulation infrastructure. The results show a fairly narrow overall performance deviation in response to significant variations in key timing parameters, and the power consumption experiments identify the key power component that is mostly affected with STT-MRAM.
- [1] . 2012. Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU. In Proceedings of the IEEE International Electron Devices Meeting (IEDM’12).Google Scholar
Cross Ref
- [2] . 2016. Performance impact of a slower main memory: A case study of STT-MRAM in HPC. In Proceedings of the 2nd International Symposium on Memory Systems
(MEMSYS’16) . Google ScholarDigital Library
- [3] . 2010. Numerical analysis of typical STT-MTJ stacks for 1T-1R memory arrays. In Proceedings of the IEEE International Electron Devices Meeting (IEDM’10).Google ScholarCross Ref
- [4] . 2020. Secure STT-MRAM bit-cell design resilient to differential power analysis attacks. IEEE Trans. VLSI Syst. 28, 1 (2020), 263–272.Google ScholarCross Ref
- [5] . 2015. DRAM refresh mechanisms, penalties, and trade-offs. IEEE Trans. Comput. 658, 1 (2015), 108–121. Google ScholarDigital Library
- [6] . 2014. Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE’14). 1–6. Google ScholarDigital Library
- [7] . 2010. Understanding the impact of emerging non-volatile memories on high-performance, IO-Intensive computing. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC’10). Google ScholarDigital Library
- [8] . 2007. ADTSC Nuclear Weapons Highlights: Facilitating High Throughput ASC Calculations. Technical Report LALP-07-041, Los Alamos National Laboratory, Los Alamos, NM.Google Scholar
- [9] . 2008. Application MTTFE vs. Platform MTTF: A fresh perspective on system reliability and application throughput for computations at scale. In Proceedings of the Workshop on Resiliency in High Performance Computing. Google ScholarDigital Library
- [10] . 1991. Giant magnetoresistive in soft ferromagnetic multilayers. Phys. Rev. B (1991).Google ScholarCross Ref
- [11] . 2012. NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans. Comput.-aid. Des. Integr. Circ. Syst. 31, 7 (2012), 994–1007. Google ScholarDigital Library
- [12] . 2002. a survey of rollback-recovery protocols in message-passing systems. ACM Comput. Surv. (2002). Google ScholarDigital Library
- [13] 2015. Everspin Enhances RIM Smart Meters with Instantly Non-volatile, Low-energy MRAM Memory. Retrieved from http://www.everspin.com/everspin-embedded-mram.Google Scholar
- [14] 2016. Everspin Displays Both the 1Gb DDR4 Perpendicular ST-MRAM Device and a 1GByte DDR3 Memory Module (DIMM) at Stand A3-545. Retrieved from https://www.everspin.com/news/everspin-previews-upcoming-products-electronica.Google Scholar
- [15] . 2009. Increasing fault resiliency in a message-passing environment. Technical Report, Sandia National Laboratories.Google Scholar
- [16] . 2010. Negative-resistance read and write schemes for STT-MRAM in 0.13um CMOS. In Proceedings of the IEEE International Solid State Circuits Conference.Google Scholar
- [17] . 2006. Berkeley Lab Checkpoint/Restart (BLCR) for Linux Clusters. J. Phys.46 (2006).Google Scholar
- [18] . 2006. SPEC CPU2006 benchmark descriptions. SIGARCH Comput. Archit. News34 (2006), 1–17. Google ScholarDigital Library
- [19] . 2005. A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. In Proceedings of the IEEE International Electron Devices Meeting.Google ScholarCross Ref
- [20] . 2019. Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications. In Proceedings of the IEEE International Electron Devices Meeting (IEDM’19). 2.6.1–2.6.4.Google ScholarCross Ref
- [21] . 2012. Cosmic rays don’t strike twice: Understanding the nature of DRAM errors and the implications for system design. In Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’12). Google ScholarDigital Library
- [22] . 2010. A perpendicular-anisotropy cofeb–mgo magnetic tunnel junction. In Nature Materials, Vol. 9. 721–724.Google Scholar
- [23] . 2015. Intel® 64 and IA-32 Architectures Optimization Reference Manual.Google Scholar
- [24] . 2017. Intel 64 and IA-32 Architectures Software Developer Manuals.Google Scholar
- [25] . 2015. 2013 International Technology Roadmap for Semiconductors. Retrieved from http://www.itrs.net/Links/2013ITRS/Home2013.htm.Google Scholar
- [26] . 2009. The Memory System: You Can’t Avoid It; You Can’t Ignore It; You Can’t Fake It. M. Morgan & Claypool Publishers, Reading, MA. Google ScholarDigital Library
- [27] . 2018. Design of High-performance, Resilient, STT-MRAM-based Main Memory. Retrieved from https://domino.research.ibm.com/library/cyberdig.nsf/papers/.Google Scholar
- [28] . 2016. improving read performance of STT-MRAM based main memories through smash read and flexible read. In Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC’16).Google ScholarDigital Library
- [29] . 2012. cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs. In Proceedings of the 49th ACM/EDAC/IEEE Design Automation Conference (DAC’12). Google ScholarDigital Library
- [30] . 2012. Evaluating row buffer locality in future non-volatile main memories. Safari Technical Report No. 2012-002.Google Scholar
- [31] . 2000. Current-driven magnetization reversal and spin-wave excitations in co \(/\)Cu \(/\)Co pillars. Phys. Rev. Lett. 84, 14 (2000), 3149–3152.Google ScholarCross Ref
- [32] . 2013. Magnetic random access memory. US Patent App. 13/768,858.
Google Scholar - [33] . 2013. Magneto-resistive memory device including source line voltage generator. US Patent App. 13/832,101.
Google Scholar - [34] . 2014. flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. In Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture (ISCA’14). Google ScholarDigital Library
- [35] . 2008. exascale computing study: Technology challenges in achieving exascale systems.Google Scholar
- [36] . 2017. Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’17). 1–4.Google ScholarCross Ref
- [37] . 2013. evaluating STT-RAM as an energy-efficient main memory alternative. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’13).Google ScholarCross Ref
- [38] . 2012. identifying opportunities for byte-addressable non-volatile memory in extreme-scale scientific applications. In Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS’12). Google ScholarDigital Library
- [39] . 2011. performance, power, and reliability tradeoffs of STT-RAM cell subject to architecture-level requirement. IEEE Trans. Magn. 47, 10 (2011), 2356–2359.Google ScholarCross Ref
- [40] . 2011. STT-RAM based energy-efficiency hybrid cache for CMPs. In Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-chip (VLSI-SoC’11).Google ScholarCross Ref
- [41] . 2012. RAIDR: Retention-aware intelligent DRAM refresh. In Proceedings of the 39th Annual International Symposium on Computer Architecture. Google ScholarDigital Library
- [42] . 2013. Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. In Proceedings of the IEEE 19th International Symposium on High Performance Computer Architecture. Google ScholarDigital Library
- [43] . 2015. Reverse engineering intel last-level cache complex addressing using performance counters. Research in Attacks, Intrusions and Defenses. 48–65. Google ScholarDigital Library
- [44] . 1996. lmbench: Portable tools for performance analysis. In Proceedings of the Annual Conference on USENIX Annual Technical Conference
(ATEC’96 ). Google ScholarDigital Library - [45] . 2009. CACTI 6.0: A Tool to Understand Large Caches. HP Technical Report HPL-2009-85 (2009).Google Scholar
- [46] . 2009. a 90nm 12ns 32Mb 2T1MTJ MRAM. In Proceedings of the IEEE International Solid-state Circuits Conference.Google ScholarCross Ref
- [47] . 2013. A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors. In Proceedings of the Symposium on VLSI Technology (VLSIT’13).Google Scholar
- [48] . 2016. Dependence of voltage and size on write error rates in spin-transfer torque magnetic random-access memory. IEEE Magn. Lett. 7 (2016), 1–4.Google ScholarCross Ref
- [49] . 2014. resistive memory device, system including the same and method of reading data in the same.
US Patent App. 14/094,021. Google Scholar - [50] . 2007. Modeling the impact of checkpoints on next-generation systems. In Proceedings of the 24th IEEE Conference on Mass Storage Systems and Technologies. Google ScholarDigital Library
- [51] . 2015. Device/Circuit/Architecture co-design of reliable STT-MRAM. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition.Google ScholarCross Ref
- [52] . 2012. NVMain: An architectural-level main memory simulator for emerging non-volatile memories. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI. Google ScholarDigital Library
- [53] . 2017. 23.5 a 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture. In Proceedings of the IEEE International Solid-state Circuits Conference (ISSCC’17).Google ScholarCross Ref
- [54] . 2011. DRAMSim2: A cycle accurate memory system simulator. IEEE Comput. Arch. Lett. 10, 1 (2011), 16–19. Google ScholarDigital Library
- [55] . 2018. Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node. In Proceedings of the IEEE International Electron Devices Meeting (IEDM’18). 18.3.1–18.3.4.Google ScholarCross Ref
- [56] . 2011. 240pin Registered DIMM Based on 2Gb d-die. Retrieved from https://www.sam-sung.com/semiconductor/global.semi/file/resource/2017/11/ds_ddr3_2gb_d-die_based_1_35v_rdimm_rev12-2.pdf.Google Scholar
- [57] . 2013. ZSim: Fast and accurate microarchitectural simulation of thousand-core systems. In Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA’13). Google ScholarDigital Library
- [58] . 2009. DRAM errors in the wild: A large-scale field study. In Proceedings of the 11th International Joint Conference on Measurement and Modeling of Computer Systems. Google ScholarDigital Library
- [59] . 2011. relaxing non-volatility for fast and energy-efficient STT-RAM caches. In Proceedings of the IEEE 17th International Symposium on High Performance Computer Architecture (HPCA’11). Google ScholarDigital Library
- [60] . 2011. Race to exascale: Opportunities and challenges. In Proceedings ofthe 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). Google ScholarDigital Library
- [61] . 1996. giant magnetoresistive spin valve bridge sensor. IEEE Trans. Magn. 32, 2 (1996), 366–371.Google ScholarCross Ref
- [62] . 2012. A study of DRAM failures in the field. In Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis. Google ScholarDigital Library
- [63] . 2013. feng shui of supercomputer memory: Positional effects in DRAM and SRAM faults. In Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis. Google ScholarDigital Library
- [64] . 2010. A decadal DOE plan for providing exascale applications and technologies for DOE mission needs. Presentation at Advanced Simulation and Computing Principal Investigators Meeting.Google Scholar
- [65] . 2009. a novel architecture of the 3D stacked MRAM L2 cache for CMPs. In Proceedings of the IEEE 15th International Symposium on High Performance Computer Architecture (HPCA’09).Google ScholarCross Ref
- [66] . 2011. multi retention level STT-RAM cache designs with a dynamic refresh scheme. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). Google ScholarDigital Library
- [67] . 2014. evaluation of emerging memory technologies for HPC, data intensive applications. In Proceedings of the IEEE International Conference on Cluster Computing (CLUSTER’14).Google ScholarCross Ref
- [68] . 2017. Top500 Supercomuter Sites. Retrieved from http://www.top500.org/.Google Scholar
- [69] . 2015. Opportunities for nonvolatile memory systems in extreme-scale high performance computing. Comput. Sci. Eng. 17, 2 (2015), 73–82. Google ScholarDigital Library
- [70] . 2005. DRAMsim: A memory system simulator. SIGARCH Comput. Archit. News 33, 4 (2005). Google ScholarDigital Library
- [71] . 2014. Enabling high-performance LPDDRx-compatible MRAM. In Proceedings of the International Symposium on Low Power Electronics and Design(
ISLPED’14 ). Google ScholarDigital Library - [72] . 1995. Hitting the memory wall: Implications of the obvious. SIGARCH Comput. Archit. News 23–1 (1995), 20–24. Google ScholarDigital Library
- [73] . 2011. modeling, architecture, and applications for emerging memory technologies. IEEE Des. Test Comput. (2011). Google ScholarDigital Library
- [74] . 2009. energy reduction for STT-RAM using early write termination. In Proceedings of the IEEE/ACM International Conference on Computer-aided Design.Google ScholarDigital Library
Index Terms
- Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation
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