Skandha Deepsita S
Abstract
The approximate hardware design can save huge energy at the cost of errors incurred in the design. This article proposes the approximate algorithm for low-power compressors, utilized to build approximate multiplier with low energy and acceptable error profiles. This article presents two design approaches (DA1 and DA2) for higher bit size approximate multipliers. The proposed multiplier of DA1 have no propagation of carry signal from LSB to MSB, resulted in a very high-speed design. The increment in delay, power, and energy are not exponential with increment of multiplier size (n) for DA1 multiplier. It can be observed that the maximum combinations lie in the threshold Error Distance of 5% of the maximum value possible for any particular multiplier of size n. The proposed 4-bit DA1 multiplier consumes only 1.3 fJ of energy, which is 87.9%, 78%, 94%, 67.5%, and 58.9% less when compared to M1, M2, LxA, MxA, accurate designs respectively. The DA2 approach is recursive method, i.e., n-bit multiplier built with n/2-bit sub-multipliers. The proposed 8-bit multiplication has 92% energy savings with Mean Relative Error Distance (MRED) of 0.3 for the DA1 approach and at least 11% to 40% of energy savings with MRED of 0.08 for the DA2 approach. The proposed multipliers are employed in the image processing algorithm of DCT, and the quality is evaluated. The standard PSNR metric is 55 dB for less approximation and 35 dB for maximum approximation.
- [1] . 2018. Low-power approximate multipliers using encoded partial products and approximate compressors. IEEE journal on Emerging and Selected Topics in Circuits and Systems 8, 3 (2018), 404–416.Google Scholar
- [2] . 2018. Low-Power approximate multipliers using encoded partial products and approximate compressors. IEEE J. Emerg. Select. Top. Circ. Syst. (2018).Google ScholarCross Ref
- [3] . 2013. ACMA: Accuracy-configurable multiplier architecture for error-resilient system-on-chip. In 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, 1–6.Google Scholar
- [4] . 2014. Power-and area-efficient approximate wallace tree multiplier for error-resilient systems. In Fifteenth International Symposium on Quality Electronic Design. IEEE, 263–269.Google Scholar
- [5] . 2013. Energy-efficient recognition and mining processor using scalable effort design. In Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1–4.Google ScholarCross Ref
- [6] . 2014. Scalable effort hardware design. IEEE Trans. VLSI Syst. 22, 9 (2014), 2004–2016.Google ScholarCross Ref
- [7] . 2021. Reconfigurable rounding based approximate multiplier for energy efficient multimedia applications. Wireless Pers. Commun. 118, 2 (2021), 919–931.Google ScholarCross Ref
- [8] . 2020. Loba: A leading one bit based imprecise multiplier for efficient image processing. J. Electr. Test. 36 (2020), 429–437.Google ScholarCross Ref
- [9] . 2018. Multipliers with approximate 4–2 compressors and error recovery modules. IEEE Embed. Syst. Lett. 10, 1 (2018), 6–9. Google ScholarDigital Library
- [10] . 2015. DRUM: A dynamic range unbiased multiplier for approximate applications. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD’15). IEEE, 418–425. Google ScholarDigital Library
- [11] . 2011. Trading accuracy for power with an underdesigned multiplier architecture (unpublished). Google ScholarDigital Library
- [12] . 2010. Low-power high-speed multiplier for error-tolerant application. (unpublished).Google Scholar
- [13] . 2018. Sculptor: Flexible approximation with selective dynamic loop perforation. In Proceedings of the 2018 International Conference on Supercomputing. 341–351. Google ScholarDigital Library
- [14] . [n. d.]. A retrospective and prospective view of approximate computing.Google Scholar
- [15] . 2017. Design of approximate radix-4 booth multipliers for error-tolerant computing. IEEE Trans. Comput. 66, 8 (2017), 1435–1441.Google ScholarDigital Library
- [16] . 2014. Unified Mitchell-based approximation for efficient logarithmic conversion circuit. IEEE Trans. Comput. 64, 6 (2014), 1783–1797.Google Scholar
- [17] . 2010. Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. IEEE Trans. Circ. Syst. I: Regul. Pap. 57, 4 (2010), 850–862. Google ScholarDigital Library
- [18] . 1962. Computer multiplication and division using binary logarithms. IRE Transactions on Electronic Computers4 (1962), 512–517.Google ScholarCross Ref
- [19] . 2015. Design and analysis of approximate compressors for multiplication. IEEE Trans. Comput. 64, 4 (2015), 984–994.Google ScholarDigital Library
- [20] . 2015. Energy-Efficient approximate multiplication for digital signal processing and classification applications. IEEE Trans. VLSI Syst. 23, 6 (2015), 1180–1184. https://doi.org/10.1109/TVLSI.2014.2333366Google ScholarDigital Library
- [21] . 2016. Architectural-space exploration of approximate multipliers. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD’16), 1–8. Google ScholarDigital Library
- [22] . 2018. Minimally biased multipliers for approximate integer and floating-point multiplication. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 37, 11 (2018), 2623–2635.Google ScholarCross Ref
- [23] . 2014. Paraprox: Pattern-based approximation for data parallel applications. In Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems. 35–50. Google ScholarDigital Library
- [24] . 2017. LETAM: A low energy truncation-based approximate multiplier. Comput. Electr. Eng. 63 (2017), 1–17. Google ScholarDigital Library
- [25] . 2014. Image processing using approximate datapath units (unpublished).Google Scholar
- [26] . 2018. Power efficient approximate booth multiplier. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’18). IEEE, 1–4.Google ScholarCross Ref
- [27] . 2015. Computing approximately, and efficiently. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE’15). IEEE, 748–751. Google ScholarDigital Library
- [28] . 2020. Hybrid partial product-based high-performance approximate recursive multipliers. IEEE Trans. Emerg. Top. Comput. (2020).Google Scholar
- [29] . 2015. Approximate compressors for error-resilient multiplier design (unpublished).Google Scholar
- [30] . 2016. RoBA multiplier: A rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing. IEEE Trans. VLSI Syst. 25, 2 (2016), 393–401. Google ScholarDigital Library
Index Terms
- Energy Efficient Error Resilient Multiplier Using Low-power Compressors
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