research-article

Functionality matters in netlist representation learning

Authors:

Guangliang Zhang,

Yu HuangAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 61 - 66

https://doi.org/10.1145/3489517.3530410

Published: 23 August 2022 Publication History

Abstract

Learning feasible representation from raw gate-level netlists is essential for incorporating machine learning techniques in logic synthesis, physical design, or verification. Existing message-passing-based graph learning methodologies focus merely on graph topology while overlooking gate functionality, which often fails to capture underlying semantic, thus limiting their generalizability. To address the concern, we propose a novel netlist representation learning framework that utilizes a contrastive scheme to acquire generic functional knowledge from netlists effectively. We also propose a customized graph neural network (GNN) architecture that learns a set of independent aggregators to better cooperate with the above framework. Comprehensive experiments on multiple complex real-world designs demonstrate that our proposed solution significantly outperforms state-of-the-art netlist feature learning flows.

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Cited By

Nguyen TJu YYoon DChoi HNakamura YWang Y(2025)Learning Gate-level Netlist Testability in the Presence of Unknowns through Graph Neural NetworksProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697753(622-627)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697753
Fang WLiu SZhang HXie ZNakamura YWang Y(2025)A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design TasksProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697597(505-512)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697597
Khan SShi ZZheng ZLi MXu QNakamura YWang Y(2025)DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled RepresentationsProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697594(498-504)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697594
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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Nguyen TJu YYoon DChoi HNakamura YWang Y(2025)Learning Gate-level Netlist Testability in the Presence of Unknowns through Graph Neural NetworksProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697753(622-627)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697753
Fang WLiu SZhang HXie ZNakamura YWang Y(2025)A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design TasksProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697597(505-512)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697597
Khan SShi ZZheng ZLi MXu QNakamura YWang Y(2025)DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled RepresentationsProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697594(498-504)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697594
Wang ZBai CHe ZZhang GXu QHo THuang YYu B(2025)FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343446444:1(227-240)Online publication date: Jan-2025
https://doi.org/10.1109/TCAD.2024.3434464
Khan SShi ZLi MXu Q(2024)DeepSeq: Deep Sequential Circuit Learning2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546639(1-2)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546639
Lu YRen HHsiao HLim S(2024)GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer LearningACM Transactions on Design Automation of Electronic Systems10.1145/363646129:2(1-17)Online publication date: 14-Feb-2024
https://dl.acm.org/doi/10.1145/3636461
Dinh TDo T(2024)Graph-Based Ranking Techniques for Improving VLSI Placement2024 IEEE 15th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)10.1109/UEMCON62879.2024.10754775(715-719)Online publication date: 17-Oct-2024
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Jiang ZJi XHe YShen H(2024)HWSim: Hardware Similarity Learning for Intellectual Property Piracy Detection2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558324(1-5)Online publication date: 19-May-2024
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Peng XSong XZou Y(2024)PreRoutSGAT: Pre-Routing Timing Prediction Based on Graph Neural Network with Global Attention2024 6th International Conference on Circuits and Systems (ICCS)10.1109/ICCS62517.2024.10846089(310-315)Online publication date: 20-Sep-2024
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