research-article

HIMap: a heuristic and iterative logic synthesis approach

Authors:

Yupeng WanAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 415 - 420

https://doi.org/10.1145/3489517.3530460

Published: 23 August 2022 Publication History

Abstract

Recently, many models show their superiority in sequence and parameter tuning. However, they usually generate non-deterministic flows and require lots of training data. We thus propose a heuristic and iterative flow, namely HIMap, for deterministic logic synthesis. In which, domain knowledge of the functionality and parameters of synthesis operators and their correlations to netlist PPA is fully utilized to design synthesis templates for various objetives. We also introduce deterministic and effective heuristics to tune the templates with relatively fixed operator combinations and iteratively improve netlist PPA. Two nested iterations with local searching and early stopping can thus generate dynamic sequence for various circuits and reduce runtime. HIMap improves 13 best results of the EPFL combinational benchmarks for delay (5 for area). Especially, for several arithmetic benchmarks, HIMap significantly reduces LUT-6 levels by 11.6 ~ 21.2% and delay after P&R by 5.0 ~ 12.9%.

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Cited By

Chen LLi XDimitrios TWang ZBai YYuan M(2024)A General Framework for Efficient Logic Synthesis2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617733(361-362)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617733
Opara AKubica M(2023)Technology Mapping of Multi–Output Functions Leading to the Reduction of Dynamic Power Consumption in FPGASInternational Journal of Applied Mathematics and Computer Science10.34768/amcs-2023-002033:2(267-284)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.34768/amcs-2023-0020
Zang XChen LLi XThong WSheng WYoung EWong MThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification SystemsProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590289(357-361)Online publication date: 5-Jun-2023
https://dl.acm.org/doi/10.1145/3583781.3590289
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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

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Publication History

Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Chen LLi XDimitrios TWang ZBai YYuan M(2024)A General Framework for Efficient Logic Synthesis2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617733(361-362)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617733
Opara AKubica M(2023)Technology Mapping of Multi–Output Functions Leading to the Reduction of Dynamic Power Consumption in FPGASInternational Journal of Applied Mathematics and Computer Science10.34768/amcs-2023-002033:2(267-284)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.34768/amcs-2023-0020
Zang XChen LLi XThong WSheng WYoung EWong MThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification SystemsProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590289(357-361)Online publication date: 5-Jun-2023
https://dl.acm.org/doi/10.1145/3583781.3590289
Yuan JWang PYe JYuan MHao JYan J(2023)EasySO: Exploration-enhanced Reinforcement Learning for Logic Synthesis Sequence Optimization and a Comprehensive RL Environment2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323973(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323973
Li XChen LZhang JWen SSheng WHuang YYuan M(2023)EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323902(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323902
Pei ZLiu FHe ZChen GZheng HZhu KYu B(2023)AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323856(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323856
Wang PLu ALi XYe JChen LYuan MHao JYan J(2023)EasyMap: Improving Technology Mapping via Exploration-Enhanced Heuristics and Adaptive Sequencing2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323703(01-09)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323703
Feng CLyu WChen ZYe JYuan MHao JMitra TYoung EXiong J(2022)Batch Sequential Black-Box Optimization with Embedding Alignment Cells for Logic SynthesisProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549363(1-9)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3549363

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