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NovelRewrite: node-level parallel AIG rewriting

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Evangeline F. Y. YoungAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 427 - 432

https://doi.org/10.1145/3489517.3530462

Published: 23 August 2022 Publication History

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Abstract

Logic rewriting is an important part in logic optimization. It rewrites a circuit by replacing local subgraphs with logically equivalent ones, so that the area and the delay of the circuit can be optimized. This paper introduces a parallel AIG rewriting algorithm with a new concept of logical cuts. Experiments show that this algorithm implemented with one GPU can be on average 32X faster than the logic rewriting in the logic synthesis tool ABC on large benchmarks. Compared with other logic rewriting acceleration works, ours has the best quality and the shortest running time.

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Cited By

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Costamagna ACalvino AMishchenko ADe Micheli GNakamura YWang Y(2025)Area-Oriented Optimization After Standard-Cell MappingProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697722(1112-1119)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697722
Liu TSun YChen LLi XYuan MYoung E(2025)A Unified Parallel Framework for LUT Mapping and Logic OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.342907944:1(214-226)Online publication date: Jan-2025
https://doi.org/10.1109/TCAD.2024.3429079
Qu NTian CDuan ZDe V(2024)DACPara: A Divide-and-Conquer Parallel Approach for High-Quality Logic Rewriting in Large-Scale CircuitsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655678(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3655678
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Published In

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Costamagna ACalvino AMishchenko ADe Micheli GNakamura YWang Y(2025)Area-Oriented Optimization After Standard-Cell MappingProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697722(1112-1119)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697722
Liu TSun YChen LLi XYuan MYoung E(2025)A Unified Parallel Framework for LUT Mapping and Logic OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.342907944:1(214-226)Online publication date: Jan-2025
https://doi.org/10.1109/TCAD.2024.3429079
Qu NTian CDuan ZDe V(2024)DACPara: A Divide-and-Conquer Parallel Approach for High-Quality Logic Rewriting in Large-Scale CircuitsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655678(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3655678
Li LLi RHa Y(2023)A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325174142:11(3972-3984)Online publication date: 19-Oct-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3251741
Liu TYoung E(2023)Rethinking AIG Resynthesis in Parallel2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247961(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247961

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Optimized reversible binary-coded decimal adders

Hardware Designs for Decimal Floating-Point Addition and Related Operations

Logic Networks of Carry-Save Adders

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