research-article

Floorplanning with graph attention

Authors:

Li ShangAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 1303 - 1308

https://doi.org/10.1145/3489517.3530484

Published: 23 August 2022 Publication History

Abstract

Floorplanning has long been a critical physical design task with high computation complexity. Its key objective is to determine the initial locations of macros and standard cells with optimized wirelength for a given area constraint. This paper presents Flora, a graph attention-based floorplanner to learn an optimized mapping between circuit connectivity and physical wirelength, and produce a chip floorplan using efficient model inference. Flora has been integrated with two state-of-the-art mixed-size placers. Experimental studies using both academic benchmarks and industrial designs demonstrate that compared to state-of-the-art mixed-size placers alone, Flora improves placement runtime by 18%, with 2% wirelength reduction on average.

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Cited By

Yu SCensor YLuo G(2025)Floorplanning With I/O Assignment via Feasibility-Seeking and Superiorization MethodsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.340810644:1(317-330)Online publication date: Jan-2025
https://doi.org/10.1109/TCAD.2024.3408106
Yao WLin YLi L(2025)Learning placement order for constructive floorplanningIntegration, the VLSI Journal10.1016/j.vlsi.2024.102293100:COnline publication date: 1-Jan-2025
https://dl.acm.org/doi/10.1016/j.vlsi.2024.102293
Yang BXu QGeng HChen SKang Y(2024)Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning Reasoner2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546767(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546767
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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 August 2022

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National Natural Science Foundation of China under Grant

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DAC '22

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SIGDA

DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

Yu SCensor YLuo G(2025)Floorplanning With I/O Assignment via Feasibility-Seeking and Superiorization MethodsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.340810644:1(317-330)Online publication date: Jan-2025
https://doi.org/10.1109/TCAD.2024.3408106
Yao WLin YLi L(2025)Learning placement order for constructive floorplanningIntegration, the VLSI Journal10.1016/j.vlsi.2024.102293100:COnline publication date: 1-Jan-2025
https://dl.acm.org/doi/10.1016/j.vlsi.2024.102293
Yang BXu QGeng HChen SKang Y(2024)Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning Reasoner2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546767(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546767
Zhao XWang TJiao RGuo X(2024)Standard Cells Do Matter: Uncovering Hidden Connections for High-Quality Macro Placement2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546560(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546560
Yang BXu QGeng HChen SYu BKang Y(2024)Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience ReplayACM Transactions on Design Automation of Electronic Systems10.1145/365345329:3(1-17)Online publication date: 3-May-2024
https://dl.acm.org/doi/10.1145/3653453
Liu YZhou HWang JYang FZeng XShang L(2024)Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary ConditionsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.336366632:5(810-822)Online publication date: May-2024
https://doi.org/10.1109/TVLSI.2024.3363666
Wu HHuang ZLi XZhu W(2024)AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RLIntegration10.1016/j.vlsi.2024.10221198(102211)Online publication date: Sep-2024
https://doi.org/10.1016/j.vlsi.2024.102211
Lai YLiu JTang ZWang BHao JLuo PKrause ABrunskill ECho KEngelhardt BSabato SScarlett J(2023)ChiPFormerProceedings of the 40th International Conference on Machine Learning10.5555/3618408.3619165(18346-18364)Online publication date: 23-Jul-2023
https://dl.acm.org/doi/10.5555/3618408.3619165
Zhao DYuan SSun YTu SXu L(2023)DeepTH: Chip Placement with Deep Reinforcement Learning Using a Three-Head Policy Network2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137100(1-2)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137100
Yu SCensor YJiang MLuo G(2023)Per-RMAP: Feasibility-Seeking and Superiorization Methods for Floorplanning with I/O Assignment2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218694(286-291)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218694
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