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Xplace: an extremely fast and extensible global placement framework

Published: 23 August 2022 Publication History

Abstract

Placement serves as a fundamental step in VLSI physical design. Recently, GPU-based global placer DREAMPlace[1] demonstrated its superiority over CPU-based global placers. In this work, we develop an extremely fast GPU accelerated global placer Xplace which achieves around 2x speedup with better solution quality compared to DREAMPlace. We also plug a novel Fourier neural network into Xplace as an extension to further improve the solution quality. We believe this work not only proposes a new, fast, extensible placement framework but also illustrates a possibility to incorporate a neural network component into a GPU accelerated analytical placer.

References

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  • (2025)Analytical Heterogeneous Die-to-Die 3-D Placement With MacrosIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344471644:2(402-415)Online publication date: Feb-2025
  • (2025)DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343652144:2(696-708)Online publication date: Feb-2025
  • (2025)A Unified Parallel Framework for LUT Mapping and Logic OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.342907944:1(214-226)Online publication date: Jan-2025
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cover image ACM Conferences
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference
July 2022
1462 pages
ISBN:9781450391429
DOI:10.1145/3489517
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 August 2022

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Cited By

View all
  • (2025)Analytical Heterogeneous Die-to-Die 3-D Placement With MacrosIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344471644:2(402-415)Online publication date: Feb-2025
  • (2025)DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343652144:2(696-708)Online publication date: Feb-2025
  • (2025)A Unified Parallel Framework for LUT Mapping and Logic OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.342907944:1(214-226)Online publication date: Jan-2025
  • (2025)An analytical placement algorithm with looking-ahead routing topology optimizationIntegration10.1016/j.vlsi.2024.102264100(102264)Online publication date: Jan-2025
  • (2024)GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer LearningACM Transactions on Design Automation of Electronic Systems10.1145/363646129:2(1-17)Online publication date: 14-Feb-2024
  • (2024)Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334729343:6(1624-1637)Online publication date: Jun-2024
  • (2024)Xplace: An Extremely Fast and Extensible Placement FrameworkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334629143:6(1872-1885)Online publication date: Jun-2024
  • (2024)TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based DesignProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473978(312-318)Online publication date: 22-Jan-2024
  • (2024)FineMap: A Fine-Grained GPU-Parallel LUT Mapping EngineProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473941(392-397)Online publication date: 22-Jan-2024
  • (2024)iPD: An Open-Source Intelligent Physical Design ToolchainProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473932(83-88)Online publication date: 22-Jan-2024
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