research-article

DeepGate: learning neural representations of logic gates

Authors:

Qiang XuAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 667 - 672

https://doi.org/10.1145/3489517.3530497

Published: 23 August 2022 Publication History

Abstract

Applying deep learning (DL) techniques in the electronic design automation (EDA) field has become a trending topic. Most solutions apply well-developed DL models to solve specific EDA problems. While demonstrating promising results, they require careful model tuning for every problem. The fundamental question on "How to obtain a general and effective neural representation of circuits?" has not been answered yet. In this work, we take the first step towards solving this problem. We propose DeepGate, a novel representation learning solution that effectively embeds both logic function and structural information of a circuit as vectors on each gate. Specifically, we propose transforming circuits into unified and-inverter graph format for learning and using signal probabilities as the supervision task in DeepGate. We then introduce a novel graph neural network that uses strong inductive biases in practical circuits as learning priors for signal probability prediction. Our experimental results show the efficacy and generalization capability of DeepGate.

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Cited By

Khan SShi ZLi MXu Q(2024)DeepSeq: Deep Sequential Circuit Learning2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546639(1-2)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546639
Zhong RYe JTang ZKai SYuan MHao JYan JWooldridge MDy JNatarajan S(2024)PreRoutGNN for timing prediction with order preserving partitionProceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence and Thirty-Sixth Conference on Innovative Applications of Artificial Intelligence and Fourteenth Symposium on Educational Advances in Artificial Intelligence10.1609/aaai.v38i15.29653(17087-17095)Online publication date: 20-Feb-2024
https://dl.acm.org/doi/10.1609/aaai.v38i15.29653
Sengupta PTyagi AHu JRajan VMostafa HMajumdar SAmrouch HHu JGarg SLin Y(2024)MinBLoG: Minimization of Boolean Logic Functions using Graph Attention NetworkProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685962(1-8)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685962
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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

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SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA

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Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference

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Cited By

Khan SShi ZLi MXu Q(2024)DeepSeq: Deep Sequential Circuit Learning2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546639(1-2)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546639
Zhong RYe JTang ZKai SYuan MHao JYan JWooldridge MDy JNatarajan S(2024)PreRoutGNN for timing prediction with order preserving partitionProceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence and Thirty-Sixth Conference on Innovative Applications of Artificial Intelligence and Fourteenth Symposium on Educational Advances in Artificial Intelligence10.1609/aaai.v38i15.29653(17087-17095)Online publication date: 20-Feb-2024
https://dl.acm.org/doi/10.1609/aaai.v38i15.29653
Sengupta PTyagi AHu JRajan VMostafa HMajumdar SAmrouch HHu JGarg SLin Y(2024)MinBLoG: Minimization of Boolean Logic Functions using Graph Attention NetworkProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685962(1-8)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685962
Sengupta PTyagi AHu JRajan VMostafa HMajumdar S(2024)MinBLoG: Minimization of Boolean Logic Functions using Graph Attention Network2024 ACM/IEEE 6th Symposium on Machine Learning for CAD (MLCAD)10.1109/MLCAD62225.2024.10740246(1-8)Online publication date: 9-Sep-2024
https://doi.org/10.1109/MLCAD62225.2024.10740246
Das SPatel HKarfa CBellamkonda KReddy RPuri DJain ASur APrajapati P(2024)RTL Simulation Acceleration with Machine Learning Models2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528688(1-7)Online publication date: 3-Apr-2024
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Xue ZLiu YYe YChen TYan HShi L(2024)Aging-Aware Logic Restructure Acceleration Based on Heterogeneous Graph Learning2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617843(480-485)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617843
Jiang ZJi XHe YShen H(2024)HWSim: Hardware Similarity Learning for Intellectual Property Piracy Detection2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558324(1-5)Online publication date: 19-May-2024
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Zhu KZhang RHe QKim T(2024)Efficient Sublogic-Cone-Based Switching Activity Estimation Using Correlation FactorProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473841(638-643)Online publication date: 22-Jan-2024
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Li ZYang LLou M(2024)DAGNN-RE: Directed Acyclic Graph Neural Network for Functional Reverse Engineering of Gate-Level NetlistIntegration10.1016/j.vlsi.2024.102343(102343)Online publication date: Dec-2024
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Aghamohammadi YRezaei A(2024)Machine Learning-Based Security Evaluation and Overhead Analysis of Logic LockingJournal of Hardware and Systems Security10.1007/s41635-024-00144-88:1(25-43)Online publication date: 22-Jan-2024
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