research-article

AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS

Authors:

Ru HuangAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 841 - 846

https://doi.org/10.1145/3489517.3530530

Published: 23 August 2022 Publication History

Abstract

As the timing guardband continues to increase with the continuous technology scaling, better-than-worst-case (BTWC) design has gained more and more attention. BTWC design can improve energy efficiency and/or performance by relaxing the conservative static timing constraints and exploiting the dynamic timing margin. However, to avoid potential reliability hazards, the existing dynamic timing analysis (DTA) tools have to add extra aging and variation guardbands, which are estimated under the worst-case corners of aging and variation. Such guardbanding method introduces unnecessary margin in timing analysis, thus reducing the performance and efficiency gains of BTWC designs. Therefore, in this paper, we propose AVATAR, an aging- and variation-aware dynamic timing analyzer that can perform DTA with the impact of transistor aging and random process variation. We also propose an application-based dynamic-voltage-accuracy-frequency-scaling (DVAFS) design flow based on AVATAR, which can improve energy efficiency by exploiting both dynamic timing slack (DTS) and the intrinsic error tolerance of the application. The results show that a 45.8% performance improvement and 68% power savings can be achieved by exploiting the intrinsic error tolerance. Compared with the conventional flow based on the corner-based DTA, the additional performance improvement of the proposed flow can be up to 14% or the additional power-saving can be up to 20%.

References

[1]

R. Huang, X. Jiang, S. Guo, P. Ren, P. Hao, Z. Yu, Z. Zhang, Y. Wang, and R. Wang, "Variability-and reliability-aware design for 16/14nm and beyond technology," in Proc. IEDM, 2017, pp. 12.4.1--12.4.4.

[2]

A. Rahimi, L. Benini, and R. K. Gupta, "Variability mitigation in nanometer cmos integrated systems: A survey of techniques from circuits to software," Proceedings of the IEEE, vol. 104, no. 7, pp. 1410--1448, 2016.

[3]

H. Cherupalli, R. Kumar, and J. Sartori, "Exploiting dynamic timing slack for energy efficiency in ultra-low-power embedded systems," in Proc. ISCA, 2016, p. 671--681.

[4]

J. Constantin, L. Wang, G. Karakonstantis, A. Chattopadhyay, and A. Burg, "Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment," in Proc. DATE, 2015, pp. 381--386.

[5]

T. Jia, R. Joseph, and J. Gu, "19.4 an adaptive clock management scheme exploiting instruction-based dynamic timing slack for a general-purpose graphics processor unit with deep pipeline and out-of-order execution," in Proc. ISSCC, 2019, pp. 318--320.

[6]

I. Tsiokanos, L. Mukhanov, and G. Karakonstantis, "Low-power variation-aware cores based on dynamic data-dependent bitwidth truncation," in Proc. DATE, 2019, pp. 698--703.

[7]

O. Assare and R. Gupta, "Accurate estimation of program error rate for timing-speculative processors," in Proc. DAC, 2019.

[8]

B. Moons, R. Uytterhoeven, W. Dehaene, and M. Verhelst, "Dvafs: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling," in Proc. DATE, 2017, pp. 488--493.

[9]

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. Springer Science & Business Media, 2009.

Digital Library

[10]

Z. Zhang, R. Wang, X. Shen, D. Wu, J. Zhang, Z. Zhang, J. Wang, and R. Huang, "Aging-aware gate-level modeling for circuit reliability analysis," IEEE TED, vol. 68, no. 9, pp. 4201--4207, 2021.

[11]

H. Amrouch, B. Khaleghi, A. Gerstlauer, and J. Henkel, "Reliability-aware design to suppress aging," in Proc. DAC, 2016, pp. 1--6.

Digital Library

[12]

A. B. Kahng, "New game, new goal posts: A recent history of timing closure," in Proc. DAC, 2015, pp. 1--6.

Digital Library

[13]

Z. Zhang, Z. Guo, Y. Lin, R. Wang, and R. Huang, "Eventtimer: Fast and accurate event-based dynamic timing analysis," in Proc. DATE, 2022.

[14]

S. Guo, R. Wang, Z. Yu, P. Hao, P. Ren, Y. Wang, S. Liao, C. Huang, T. Guo, A. Chen, J. Xie, and R. Huang, "Towards reliability-aware circuit design in nanoscale finfet technology: --- new-generation aging model and circuit reliability simulator," in Proc. ICCAD, 2017, pp. 780--785.

Digital Library

[15]

B. Kaczer, T. Grasser, P. J. Roussel, J. Franco, R. Degraeve, L.-A. Ragnarsson, E. Simoen, G. Groeseneken, and H. Reisinger, "Origin of nbti variability in deeply scaled pfets," in Proc. IRPS, 2010, pp. 26--32.

[16]

V. K. Chippa, S. T. Chakradhar, K. Roy, and A. Raghunathan, "Analysis and characterization of inherent application resilience for approximate computing," in Proc. DAC, 2013.

[17]

M. Gautschi, P. D. Schiavone, A. Traber, I. Loi, A. Pullini, D. Rossi, E. Flamand, F. K. Gürkaynak, and L. Benini, "Near-threshold risc-v core with dsp extensions for scalable iot endpoint devices," IEEE TVLSI, vol. 25, no. 10, pp. 2700--2713, 2017.

[18]

M. Martins, J. M. Matos, R. P. Ribas, A. Reis, G. Schlinker, L. Rech, and J. Michelsen, "Open cell library in 15nm freepdk technology," in Proc. ISQED. New York, NY, USA: Association for Computing Machinery, 2015, p. 171--178.

[19]

X. Jiang, X. Wang, R. Wang, B. Cheng, A. Asenov, and R. Huang, "Predictive compact modeling of random variations in finfet technology for 16/14nm node and beyond," in Proc. IEDM, 2015, pp. 28.3.1--28.3.4.

[20]

M. Alioto, G. Scotti, and A. Trifiletti, "A novel framework to estimate the path delay variability on the back of an envelope via the fan-out-of-4 metric," IEEE TCAS I, vol. 64, no. 8, pp. 2073--2085, 2017.

[21]

X. Jiao, M. Luo, J. H. Lin, and R. K. Gupta, "An assessment of vulnerability of hardware neural networks to dynamic voltage and temperature variations," in Proc. ICCAD, 2017, pp. 945--950.

[22]

Z. Guo, T.-W. Huang, and Y. Lin, "Heterocppr: Accelerating common path pessimism removal with heterogeneous cpu-gpu parallelism," in Proc. ICCAD, 2021, pp. 1--9.

Digital Library

Cited By

Ye YChen TGao YYan HYu BShi L(2024)Timing-Driven Technology Mapping Approximation Based on Reinforcement LearningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337901643:9(2755-2768)Online publication date: Sep-2024
https://doi.org/10.1109/TCAD.2024.3379016
Zhang ZWei RLi MLin YWang RHuang R(2023)READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323816(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323816
Jiang I(2023)Lightning Talk: All Routes to Timing Closure2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247801(1-2)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247801

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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

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Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Ye YChen TGao YYan HYu BShi L(2024)Timing-Driven Technology Mapping Approximation Based on Reinforcement LearningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.337901643:9(2755-2768)Online publication date: Sep-2024
https://doi.org/10.1109/TCAD.2024.3379016
Zhang ZWei RLi MLin YWang RHuang R(2023)READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323816(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323816
Jiang I(2023)Lightning Talk: All Routes to Timing Closure2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247801(1-2)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247801
Wang RZhang ZSun ZGuo ZLin YHuang R(2022)Cross-Layer Design for Reliability in Advanced Technology Nodes: An EDA Perspective2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)10.1109/ICSICT55466.2022.9963318(1-4)Online publication date: 25-Oct-2022
https://doi.org/10.1109/ICSICT55466.2022.9963318

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