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Don't open row: rethinking row buffer policy for improving performance of non-volatile memories

Published:23 August 2022Publication History

ABSTRACT

Among the various NVM technologies, phase-change-memory (PCM) has attracted substantial attention as a candidate to replace the DRAM for next-generation memory. However, the characteristics of PCM cause it to have much longer read and write latencies than DRAM. This paper proposes a Write-Around PCM System that addresses this limitation using two novel schemes: Pseudo-Row Activation and Direct Write. Pseudo-Row Activation provides fast row activation for PCM writes by connecting a target row to bitlines, but it does not fetch the data into the row buffer. With the Direct Write scheme, our system allows for writing operations to update the data even if the target row is in the logically closed state.

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      cover image ACM Conferences
      DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference
      July 2022
      1462 pages
      ISBN:9781450391429
      DOI:10.1145/3489517

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      • Published: 23 August 2022

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