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Write or not: programming scheme optimization for RRAM-based neuromorphic computing

Published: 23 August 2022 Publication History

Abstract

One main fault-tolerant method for a neural network accelerator based on resistive random access memory crossbars is the programming-based method, which is also known as write-and-verify (W-V). In the basic W-V scheme, all devices in crossbars are programmed repeatedly until they are close enough to their targets, which costs huge overhead. To reduce the cost, we optimize the W-V scheme by proposing a probabilistic termination criterion on a single device and a systematic optimization method on multiple devices. Furthermore, we propose a joint algorithm that assists the novel W-V scheme by incremental retraining, which further reduces the W-V cost. Compared to the basic W-V scheme, our proposed method improves the accuracy by 0.23% for ResNet18 on CIFAR10 with only 9.7% W-V cost under variation with σ = 1.2.

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P. Chi et al. PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In ISCA, pages 27--39, 2016.
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Cited By

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  • (2023)PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137266(1-6)Online publication date: Apr-2023
  • (2023)CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network AccelerationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.327287470:8(3198-3211)Online publication date: Aug-2023
  • (2023)TOSA: Tolerating Stuck-At-Faults in Edge-based RRAM Inference Accelerators2023 IEEE 29th International Conference on Parallel and Distributed Systems (ICPADS)10.1109/ICPADS60453.2023.00172(1181-1190)Online publication date: 17-Dec-2023
  • Show More Cited By

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cover image ACM Conferences
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference
July 2022
1462 pages
ISBN:9781450391429
DOI:10.1145/3489517
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 23 August 2022

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Author Tags

  1. RRAM
  2. neural network
  3. reliability
  4. variation
  5. write-and-verify

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DAC '22: 59th ACM/IEEE Design Automation Conference
July 10 - 14, 2022
California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2023)PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing Acceleration2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137266(1-6)Online publication date: Apr-2023
  • (2023)CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network AccelerationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.327287470:8(3198-3211)Online publication date: Aug-2023
  • (2023)TOSA: Tolerating Stuck-At-Faults in Edge-based RRAM Inference Accelerators2023 IEEE 29th International Conference on Parallel and Distributed Systems (ICPADS)10.1109/ICPADS60453.2023.00172(1181-1190)Online publication date: 17-Dec-2023
  • (2023)TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323889(1-9)Online publication date: 28-Oct-2023

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