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Partition and place finite element model on wafer-scale engine

Published: 23 August 2022 Publication History

Abstract

The finite element method (FEM) is a well-known technique for approximately solving partial differential equations and it finds application in various engineering disciplines. The recently introduced wafer-scale engine (WSE) has shown the potential to accelerate FEM by up to 10,000×. However, accelerating FEM to the full potential of a WSE is non-trivial. Thus, in this work, we propose a partitioning algorithm to partition a 3D finite element model into tiles. The tiles can be thought of as a special netlist and are placed onto the 2D array of a WSE by our placement algorithm. Compared to the best-known approach, our partitioning has around 5% higher accuracy, and our placement algorithm can produce around 11% shorter wirelength (L1.5-normalized) on average.

References

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Shih-Chun Chen and Yao-Wen Chang. 2017. FPGA placement and routing. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE.
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Zhisong Fu et al. 2014. Architecting the finite element method pipeline for the GPU. Journal of computational and applied mathematics (2014).
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Patrick Groeneveld et al. 2021. ISPD 2021 Wafer-Scale Physics Modeling Contest: A New Frontier for Partitioning, Placement and Routing. In Proceedings of the 2021 International Symposium on Physical Design.
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Zhuolun He et al. 2021. Physical synthesis for advanced neural network processors. In 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE.
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Bentian Jiang et al. 2020. CU. POKer: placing DNNs on wafer-scale AI accelerator with optimal kernel sizing. In Proceedings of the 39th International Conference on Computer-Aided Design.
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Chak-Wa Pui et al. 2016. RippleFPGA: A routability-driven placement for large-scale heterogeneous FPGAs. In 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE.
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Kamil Rocki et al. 2020. Fast stencil-code computation on a wafer-scale processor. arXiv preprint arXiv:2010.03660 (2020).
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Yuan Xue et al. 2017. Age-aware logic and memory co-placement for RRAM-FPGAs. In Proceedings of the 54th Annual Design Automation Conference 2017.

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cover image ACM Conferences
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference
July 2022
1462 pages
ISBN:9781450391429
DOI:10.1145/3489517
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 23 August 2022

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DAC '22
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DAC '22: 59th ACM/IEEE Design Automation Conference
July 10 - 14, 2022
California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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