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High-performance placement for large-scale heterogeneous FPGAs with clock constraints

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Yao-Wen ChangAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 643 - 648

https://doi.org/10.1145/3489517.3530567

Published: 23 August 2022 Publication History

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Abstract

With the increasing complexity of the field-programmable gate array (FPGA) architecture, heterogeneity and clock constraints have greatly challenged FPGA placement. In this paper, we present a high-performance placement algorithm for large-scale heterogeneous FPGAs with clock constraints. We first propose a connectivity-aware and type-balanced clustering method to construct the hierarchy and improve the scalability. In each hierarchy level, we develop a novel hybrid penalty and augmented Lagrangian method to formulate the heterogeneous and clock-aware placement as a sequence of unconstrained optimization subproblems and adopt the Adam method to solve each unconstrained optimization subproblem. Then, we present a matching-based IP blocks legalization to legalize the RAMs and DSPs, and a multi-stage packing technique is proposed to cluster FFs and LUTs into HCLBs. Finally, history-based legalization is developed to legalize CLBs in an FPGA. Based on the ISPD 2017 clock-aware FPGA placement contest benchmarks, experimental results show that our algorithm achieves the smallest routed wirelength for all the benchmarks among all published works in a reasonable runtime.

References

[1]

T. Chan, J. Cong, and K. Sze. Multilevel generalized force-directed method for circuit placement. In Proceedings of International Symposium on Physical design, pages 185--192, 2005.

Digital Library

Google Scholar

[2]

G. Chen, C.-W. Pui, W.-K. Chow, K.-C. Lam, J. Kuang, E. F. Young, and B. Yu. Ripplefpga: Routability-driven simultaneous packing and placement for modern fpgas. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(10):2022--2035, 2018.

Digital Library

Google Scholar

[3]

J. Chen, Z. Lin, Y.-C. Kuo, C.-C. Huang, Y.-W. Chang, S.-C. Chen, C.-H. Chiang, and S.-Y. Kuo. Clock-aware placement for large-scale heterogeneous fpgas. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(12):5042--5055, 2020.

Crossref

Google Scholar

[4]

T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. Ntuplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(7):1228--1240, 2008.

Digital Library

Google Scholar

[5]

M. R. Hestenes. Multiplier and gradient methods. Journal of optimization theory and applications, 4(5):303--320, 1969.

Google Scholar

[6]

D. P. Kingma and J. Ba. Adam: A method for stochastic optimization. arXiv preprint arXiv:1412.6980, 2014.

Google Scholar

[7]

W. Li, M. E. Dehkordi, S. Yang, and D. Z. Pan. Simultaneous placement and clock tree construction for modern fpgas. In Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 132--141, 2019.

Digital Library

Google Scholar

[8]

W. Li, S. Dhar, and D. Z. Pan. UTPlaceF: A routability-driven FPGA placer with physical and congestion aware packing. In Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2016.

Digital Library

Google Scholar

[9]

W. Li, Y. Lin, M. Li, S. Dhar, and D. Z. Pan. Utplacef 2.0: A high-performance clock-aware fpga placement engine. ACM Transactions on Design Automation of Electronic Systems, 23(4):1--23, 2018.

Google Scholar

[10]

Z. Lin, Y. Xie, G. Qian, J. Chen, S. Wang, J. Yu, and Y.-W. Chang. Timing-driven placement for fpgas with heterogeneous architectures and clock constraints. In Proceedings of Design, Automation, and Test in Europe, pages 1564--1569, 2021.

Crossref

Google Scholar

[11]

G.-J. Nam, S. Reda, C. J. Alpert, P. G. Villarrubia, and A. B. Kahng. A fast hierarchical quadratic placement algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(4):678--691, 2006.

Digital Library

Google Scholar

[12]

C.-W. Pui, G. Chen, Y. Ma, E. F. Young, and B. Yu. Clock-aware ultrascale fpga placement with machine learning routability prediction. In Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pages 929--936, 2017.

Digital Library

Google Scholar

[13]

S. Yang, C. Mulpuri, S. Reddy, M. Kalase, S. Dasasathyan, M. E. Dehkordi, M. Tom, and R. Aggarwal. Clock-aware fpga placement contest. In Proceedings of ACM International Symposium on Physical Design, pages 159--164, 2017.

Digital Library

Google Scholar

[14]

Z. Zhu, J. Chen, Z. Peng, W. Zhu, and Y.-W. Chang. Generalized augmented lagrangian and its applications to vlsi global placement. In Proceedings of ACM/ESDA/IEEE Design Automation Conference, pages 1--6, 2018.

Google Scholar

Cited By

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Gu HGu JPeng KYang JZhu ZDe V(2024)Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region ConstraintsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3663497(1-2)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3663497
Zhang BZhen LWang SYang F(2024)Integrating Operations Research into Very Large-Scale Integrated Circuits Placement Design: A ReviewAsia-Pacific Journal of Operational Research10.1142/S021759592450007641:06Online publication date: 6-Jul-2024
https://doi.org/10.1142/S0217595924500076
Kariotis KDadaliaris AKranas GDimitriou GDossis M(2024)Current Status of Analytical FPGA Placement2024 9th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)10.1109/SEEDA-CECNSM63478.2024.00015(30-35)Online publication date: 20-Sep-2024
https://doi.org/10.1109/SEEDA-CECNSM63478.2024.00015
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DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

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Gu HGu JPeng KYang JZhu ZDe V(2024)Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region ConstraintsProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3663497(1-2)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3663497
Zhang BZhen LWang SYang F(2024)Integrating Operations Research into Very Large-Scale Integrated Circuits Placement Design: A ReviewAsia-Pacific Journal of Operational Research10.1142/S021759592450007641:06Online publication date: 6-Jul-2024
https://doi.org/10.1142/S0217595924500076
Kariotis KDadaliaris AKranas GDimitriou GDossis M(2024)Current Status of Analytical FPGA Placement2024 9th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)10.1109/SEEDA-CECNSM63478.2024.00015(30-35)Online publication date: 20-Sep-2024
https://doi.org/10.1109/SEEDA-CECNSM63478.2024.00015
Li ZZhu ZHe HChen J(2024)An effective routability-driven packing algorithm for large-scale heterogeneous FPGAsIntegration, the VLSI Journal10.1016/j.vlsi.2023.10209894:COnline publication date: 4-Mar-2024
https://dl.acm.org/doi/10.1016/j.vlsi.2023.102098
Zhu ZLi YSu MZhang SSu HXiao YHe HChen JChang Y(2024)Subgraph matching-based reference placement for printed circuit board designsThe Journal of Supercomputing10.1007/s11227-024-06338-9Online publication date: 6-Jul-2024
https://doi.org/10.1007/s11227-024-06338-9
Zhu ZMei YDeng KHe HChen JYang JChang Y(2023)High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332977443:3(956-969)Online publication date: 6-Nov-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3329774

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Clock-aware placement for large-scale heterogeneous FPGAs

Clock-aware placement for large-scale heterogeneous FPGAs

High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints

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