research-article

Architecting DDR5 DRAM caches for non-volatile memory systems

Authors:

Li ZhaoAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 1057 - 1062

https://doi.org/10.1145/3489517.3530570

Published: 23 August 2022 Publication History

Abstract

With the release of Intel's Optane DIMM, Non-Volatile Memories (NVMs) are emerging as viable alternatives to DRAM memories because of the advantage of higher capacity. However, the higher latency and lower bandwidth of Optane prevent it from outright replacing DRAM. A prevailing strategy is to employ existing DRAM as a data cache for Optane, thereby achieving overall benefit in capacity, bandwidth, and latency.

In this paper, we inspect new features in DDR5 to better support the DRAM cache design for Optane. Specifically, we leverage the two-level ECC scheme, i.e., DIMM ECC and on-die ECC, in DDR5 to construct a narrower channel for tag probing and propose a new operation for fast cache replacement. Experimental results show that our proposed strategy can achieve, on average, 26% performance improvement.

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T. Lu, et al., "System measurement of Intel AEP Optane DIMM," in arXiv:2009.14469, 2020.

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Digital Library

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Cited By

Hong JKim SJang JYang JDev KYoo JMeinerzhagen P(2024)LOCo: LPDDR Optimization with Compression and IECC scheme for DNN InferenceProceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design10.1145/3665314.3670812(1-6)Online publication date: 5-Aug-2024
https://dl.acm.org/doi/10.1145/3665314.3670812
Wang XKotra JJones AXiong WJian X(2024)Counter-light Memory Encryption2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00058(724-738)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00058

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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Hong JKim SJang JYang JDev KYoo JMeinerzhagen P(2024)LOCo: LPDDR Optimization with Compression and IECC scheme for DNN InferenceProceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design10.1145/3665314.3670812(1-6)Online publication date: 5-Aug-2024
https://dl.acm.org/doi/10.1145/3665314.3670812
Wang XKotra JJones AXiong WJian X(2024)Counter-light Memory Encryption2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00058(724-738)Online publication date: 29-Jun-2024
https://doi.org/10.1109/ISCA59077.2024.00058

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