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TAIM: ternary activation in-memory computing hardware with 6T SRAM array

Authors:

Nameun Kang,

Hyungjun Kim,

Hyunmyung Oh,

Jae-Joon KimAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 1081 - 1086

https://doi.org/10.1145/3489517.3530574

Published: 23 August 2022 Publication History

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Abstract

Recently, various in-memory computing accelerators for low precision neural networks have been proposed. While in-memory Binary Neural Network (BNN) accelerators achieved significant energy efficiency, BNNs show severe accuracy degradation compared to their full precision counterpart models. To mitigate the problem, we propose TAIM, an in-memory computing hardware that can support ternary activation with negligible hardware overhead. In TAIM, a 6T SRAM cell can compute the multiplication between ternary activation and binary weight. Since the 6T SRAM cell consumes no energy when the input activation is 0, the proposed TAIM hardware can achieve even higher energy efficiency compared to BNN case by exploiting input 0's. We fabricated the proposed TAIM hardware in 28nm CMOS process and evaluated the energy efficiency on various image classification benchmarks. The experimental results show that the proposed TAIM hardware can achieve ~ 3.61× higher energy efficiency on average compared to previous designs which support ternary activation.

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Cited By

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Nguyen TLe MPham TChang I(2024)TA-Quatro: Soft Error-Resilient and Power-Efficient SRAM Cell for ADC-Less Binary Weight and Ternary Activation In-Memory ComputingElectronics10.3390/electronics1315290413:15(2904)Online publication date: 23-Jul-2024
https://doi.org/10.3390/electronics13152904

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DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 23 August 2022

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Samsung Research Funding Center
Korea government (MSIT)

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DAC '22

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SIGDA

DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Nguyen TLe MPham TChang I(2024)TA-Quatro: Soft Error-Resilient and Power-Efficient SRAM Cell for ADC-Less Binary Weight and Ternary Activation In-Memory ComputingElectronics10.3390/electronics1315290413:15(2904)Online publication date: 23-Jul-2024
https://doi.org/10.3390/electronics13152904

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Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse

IMC: energy-efficient in-memory convolver for accelerating binarized deep neural network

MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications

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