ABSTRACT
In modern VLSI designs, I/O counts have been growing continuously as the system becomes more complicated. To achieve higher routability, the hexagonal array is introduced with higher pad density and a larger pitch. However, the routing for hexagonal arrays is significantly different from that for traditional gird and staggered arrays. In this paper, we consider the Y-architecture-based flip-chip routing used for the hexagonal array. Unlike the conventional Manhattan and the X-architectures, the Y-architecture allows wires to be routed in three directions, namely, 0-, 60-, and 120-degrees. We first analyze the routing properties of the hexagonal array. Then, we propose a triangular tile model and a chord-based internal node division method that can handle both pre-assignment and free-assignment nets without wire crossing. Finally, we develop a novel dynamic programming-based bend minimization method to reduce the number of routing bends in the final solution. Experimental results show that our algorithm can achieve 100% routability with minimized total wirelength and the number of routing bends effectively.
- Algorithmic Solutions Software GmbH. 2021. LEDA: the library of efficient data types and algorithms. https://www.algorithmic-solutions.com/Google Scholar
- Yu-Jie Cai, Yang Hsu, and Yao-Wen Chang. 2021. Simultaneous pre- and free-assignment routing for multiple redistribution layers with irregular vias. In Proc. of ACM/IEEE DAC. 1147--1152.Google ScholarDigital Library
- Hongyu Chen, Chung-Kuan Cheng, Andrew B Kahng, Ion I Mandoiu, Qinke Wang, and Bo Yao. 2005. The Y architecture for on-chip interconnect: analysis and methodology. IEEE TCAD 24, 4 (2005), 588--599.Google Scholar
- Hongyu Chen, Bo Yao, Feng Zhou, and Chung-Kuan Cheng. 2003. The Y-architecture: yet another on-chip interconnect solution. In Proc. of IEEE/ACM ASP-DAC. 840--847.Google ScholarDigital Library
- Fu-Yu Chuang and Yao-Wen Chang. 2021. Optical routing considering waveguide matching constraints. In Proc. of IEEE/ACM ICCAD.Google Scholar
- Jia-Wei Fang and Yao-Wen Chang. 2008. Area-I/O flip-chip routing for chip-package codesign. In Proc. of IEEE/ACM ICCAD. 518--522.Google Scholar
- Jia-Wei Fang, Chin-Hsiung Hsu, and Yao-Wen Chang. 2009. An integer-linear-programming-based routing algorithm for flip-chip designs. IEEE TCAD 28, 1 (2009), 98--110.Google Scholar
- Jia-Wei Fang, I-Jye Lin, Yao-Wen Chang, and Jyh-Herng Wang. 2007. A network-flow-based RDL routing algorithmz for flip-chip design. IEEE TCAD 26, 8 (2007), 1417--1429.Google ScholarDigital Library
- Jia-Wei Fang, Martin D. F. Wong, and Yao-Wen Chang. 2009. Flip-chip routing with unified area-I/O pad assignments for package-board co-design. In Proc. of ACM/IEEE DAC. 336--339.Google ScholarDigital Library
- Yuan-Kai Ho, Hsu-Chieh Lee, and Yao-Wen Chang. 2013. Escape routing for staggered-pinarray PCBs. IEEE TCAD 32, 9 (2013), 1347--1356.Google Scholar
- Yuan-Kai Ho, Hsu-Chieh Lee, Webber Lee, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, and Chin-Fang Shen. 2014. Obstacle-avoiding free-assignment routing for flip-chip designs. IEEE TCAD 33, 2 (2014), 224--236.Google Scholar
- Hsu-Chieh Lee, Yao-Wen Chang, and Po-Wei Lee. 2010. Recent research development in flip-chip routing. In Proc. of IEEE/ACM ICCAD. 404--410.Google ScholarCross Ref
- Bo-Qiao Lin, Ting-Chou Lin, and Yao-Wen Chang. 2016. Redistribution layer routing for integrated fan-out wafer-level chip-scale packages. In Proc. of IEEE/ACM ICCAD. 1--8.Google ScholarDigital Library
- Chung-Wei Lin, Po-Wei Lee, Yao-Wen Chang, Chin-Fang Shen, and Wei-Chih Tseng. 2012. An efficient pre-assignment routing algorithm for flip-chip designs. IEEE TCAD 31, 6 (2012), 878--889.Google Scholar
- Ting-Chou Lin, Chia-Chih Chi, and Yao-Wen Chang. 2017. Redistribution layer routing for wafer-level integrated fan-out package-on-packages. In Proc. of IEEE/ACM ICCAD. 561--568.Google ScholarDigital Library
- Yu-Sheng Lu, Sheng-Jung Yu, and Yao-Wen Chang. 2020. A provably good wavelength-division-multiplexing-aware clustering algorithm for on-chip optical routing. In Proc. of ACM/IEEE DAC. 1--6.Google ScholarCross Ref
- Rui Shi and Chung-Kuan Cheng. 2006. Efficient escape routing for hexagonal array of high density I/Os. In Proc. of ACM/IEEE DAC. 1003--1008.Google ScholarDigital Library
- The Boost organization. 2021. Boost C++ libraries. https://www.boost.org/Google Scholar
- Albert Titus, Bhanu Jaiswal, and T Dishongh. 2004. Innovative circuit board level routing designs for BGA packages. IEEE Trans. Adv. Packag. 27, 4 (2004), 630--639.Google ScholarCross Ref
- Hsiang-Ting Wen, Yu-Jie Cai, Yang Hsu, and Yao-Wen Chang. 2020. Via-based redistribution layer routing for InFO packages with irregular pad structures. In Proc. of ACM/IEEE DAC. 1--6.Google ScholarCross Ref
- Jin-Tai Yan. 2018. Single-layer GNR routing for minimization of bending delay. IEEE TCAD 38, 11 (2018), 2099--2112.Google Scholar
- Jin-Tai Yan. 2020. Delay-constrained GNR routing for layer minimization. IEEE TVLSI 28, 11 (2020), 2356--2369.Google Scholar
- Tan Yan and Martin D. F. Wong. 2012. Correctly modeling the diagonal capacity in escape routing. IEEE TCAD 31, 2 (2012), 285--293.Google ScholarDigital Library
- Tao-Chun Yu, An-Jie Shih, and Shao-Yun Fang. 2019. Flip-chip routing with I/O planning considering practical pad assignment constraints. IEEE TVLSI 27, 8 (2019), 1921--1932.Google Scholar
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