Cited By
View all- Valente LRestuccia FRossi DKastner RBenini L(2024)TOP: Towards Open & Predictable Heterogeneous SoCsIEEE Transactions on Computers10.1109/TC.2024.344184973:12(2678-2692)Online publication date: Dec-2024
BlueScale: a scalable memory architecture for predictable real-time computing on highly integrated SoCs
Authors: 
Zhe Jiang, Kecheng Yang, Neil Audsley, Nathan Fisher, Weisong Shi, 
Zheng DongAuthors Info & Claims
Zhe Jiang, Kecheng Yang, Neil Audsley, Nathan Fisher, Weisong Shi, Zheng DongAuthors Info & ClaimsPages 1261 - 1266
Abstract
In real-time embedded computing, time-predictability and performance are required simultaneously by memory transactions. However, with increasingly more elements being integrated into hardware, memory interconnects become a critical stumbling block to satisfying timing correctness, due to lack of hardware and scheduling scalability. In this paper, we propose a new hierarchically distributed memory interconnect, BlueScale, managing memory transactions using identical Scale Elements, which ensures hardware scalability. The Scale Element introduces two nested priority queues, achieving iterative compositional scheduling for memory transactions, guaranteeing transaction tasks' scheduling schedulability. Associated with the new architecture, a theoretical model is established to improve BlueScale's real-time performance.
References
[1]
SEBASTIAN Anthony. 2017. IBM first 5nm chip. Ars Technica (2017).
[2]
ARM. 1995. AMBA AXI 5.0. https://developer.arm.com/architectures.
[3]
Neil Audsley. 2013. Memory architecture for NoC-based real-time mixed criticality systems. Proc. WMC, RTSS (2013), 37--42.
[4]
EEMBC. [n.d.]. EEMBC benchmark. https://www.eembc.org/autobench/.
[5]
Renesas Electronics. [n.d.]. Renesas: Automotive Use Cases. https://www.renesas.com/solutions/automotive.html.
[6]
Garside, Jamie and Audsely, Neil. 2013. Prefetching across a shared memory tree within a network-on-chip architecture. In IEEE Proc. SoCC.
[7]
Gomony, Garside, Akesson, Audsley, and Goossens. 2016. A globally arbitrated memory tree for mixed-time-criticality systems. IEEE TC (2016).
[8]
Manil Dev Gomony et al. 2015. A generic, scalable and globally arbitrated memory tree for shared DRAM access. In IEEE Proc. DATE.
[9]
John L Hennessy. 2011. Computer architecture: a quantitative approach.
[10]
ISO. 2018. 26262: Road vehicles-Functional safety. FDIS (2018).
[11]
Zhe Jiang et al. 2021. AXI-InterconnectRT: Towards a Real-Time AXI-Interconnect for System-on-Chips. In IEEE Proc. RTAS.
[12]
Zhe Jiang and Neil Audsley. 2018. Bluevisor: A scalable real-time hardware hypervisor for many-core embedded systems. In Proc. RTAS.
[13]
Susumu Mashimo et al. 2019. An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. In Proc. ICFPT.
[14]
Gary Plumbridge. 2014. Blueshell: a platform for rapid prototyping of multiprocessor NoCs and accelerators. Computer Architecture News (2014).
[15]
Francesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgiomaria Cicero, and Giorgio Buttazzo. 2020. AXI hyperconnect: a predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC. In IEEE Proc.DAC.
[16]
Martin Schoeberl et al. 2015. T-CREST: Time-predictable multi-core architecture for embedded systems. Journal of Systems Architecture (2015).
[17]
I. Shin and I. Lee. 2003. Periodic resource model for compositional real-time guarantees. In IEEE Proc. RTSS.
[18]
Vivado. [n.d.]. Microblaze. https://www.xilinx.com/download/vivado.html.
[19]
Haitong Wang et al. 2020. Addressing resource contention and timing predictability for multi-core architectures with memory interconnects. In RTAS.
[20]
Haitong Wang et al. 2020. Meshed Bluetree: Time-Predictable Multimemory Interconnect for Multicore Architectures. IEEE TCAD (2020).
[21]
Dawei Yang. 2021. Nebula: A Scalable and Flexible Accelerator for DNN Multi-Branch Blocks. Inform. Process. Lett. (2021).
Recommendations
A Survey of WCET Analysis of Real-Time Operating Systems
ICESS '09: Proceedings of the 2009 International Conference on Embedded Software and SystemsTiming correctness of hard real-time systems is guaranteed by schedulability analysis and worst-case execution time (WCET) analysis of programs. Traditional WCET analysis mainly deals with application programs and has achieved success in industry. ...
MDARTS: A Multiprocessor Database Architecture for Hard Real-Time Systems
Complex real-time systems need databases to support concurrent data access and provide well-defined interfaces between software modules. However, conventional database systems and prior real-time database systems do not provide the performance or ...
Comments
Information & Contributors
Information
Published In
Copyright © 2022 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 23 August 2022
Check for updates
Qualifiers
- Research-article
Conference
DAC '22
Sponsor:
Acceptance Rates
Overall Acceptance Rate 1,770 of 5,499 submissions, 32%
Upcoming Conference
DAC '25
- Sponsor:
- sigda
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations1Total Citations
- 186Total Downloads
- Downloads (Last 12 months)34
- Downloads (Last 6 weeks)3
Reflects downloads up to 05 Mar 2025
Other Metrics
Citations
Cited By
View all- Valente LRestuccia FRossi DKastner RBenini L(2024)TOP: Towards Open & Predictable Heterogeneous SoCsIEEE Transactions on Computers10.1109/TC.2024.344184973:12(2678-2692)Online publication date: Dec-2024
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in