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Secure by construction: addressing security vulnerabilities introduced during high-level synthesis: invited

Authors:

Md Rafid Muttaki,

Zahin Ibnat,

Farimah FarahmandiAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 1371 - 1374

https://doi.org/10.1145/3489517.3530674

Published: 23 August 2022 Publication History

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Abstract

Working towards a higher level of abstraction (C/C++) facilitates designers to execute and validate complex designs faster in response to highly demanding time-to-market requirements. High-Level Synthesis (HLS) is an automatic process that translates the high-level description of the design behaviors into the corresponding hardware description language (HDL) modules. However, HLS translation steps/optimizations can cause security vulnerabilities since they have not been designed with security in mind. It is very important that HLS generates functionally correct RTL in a secure manner in the first place since it is not easy to read the automatically generated codes and trace them back to the source of vulnerabilities. Even if one manages to identify and fix the security vulnerabilities in one design, the core of the HLS engine remains vulnerable. Therefore, the same vulnerabilities will appear in all other HLS generated RTL codes. This paper shows a systematic approach for identifying the source of security vulnerabilities introduced during HLS and mitigating them.

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Ibnat ZKamali HFarahmandi F(2023)Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT59622.2023.10313550(1-6)Online publication date: 3-Oct-2023
https://doi.org/10.1109/DFT59622.2023.10313550

Index Terms

Secure by construction: addressing security vulnerabilities introduced during high-level synthesis: invited
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Ibnat ZKamali HFarahmandi F(2023)Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT59622.2023.10313550(1-6)Online publication date: 3-Oct-2023
https://doi.org/10.1109/DFT59622.2023.10313550

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SecHLS: Enabling Security Awareness in High-Level Synthesis

Analyzing Security Vulnerabilities Induced by High-level Synthesis

Reliability-Aware Resource Allocation and Binding in High-Level Synthesis

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