Ken Eguro
Hongbo Rong
Hardware accelerators have been used recently to augment the compute power of data centers to improve the performance of many applications, particularly to optimize latency sensitive applications. In fact, several commercial vendors offer FPGAs in their cloud platforms. This Special Issue of TRETS presents advanced research in using FPGAs in data centers. The papers present recent research in several topics including: impact of terrestrial radiation, memory system optimization using FPGAs, use and management of network accessible FPGAs, virtualization and run-time resource management in using FPGAs, novel applications of FPGAs in data centers, FPGA IP cores for data center acceleration, latency and performance tradeoffs in using FPGAs for acceleration, and communication optimization using FPGAs.
In response to the call for papers, 21 papers were received. After a thorough review of these manuscripts following the ACM manuscript review guidelines, 13 papers were accepted. The papers are grouped into two issues. The previous issue (Issue 15:2) includes 10 papers as Part I of the special issue, and this issue includes the remaining 3 papers as Part II of the same special issue.
The paper “ Algean:AnOpenFrameworkforDeployingMachineLearningonHeterogeneousClusters” by Tarafdar et al. presents an open framework to build and deploy machine learning (ML) algorithms on a heterogeneous cluster of devices (CPUs and FPGAs). The paper “ AUnifiedFPGAVirtualizationFrameworkforGeneral-PurposeDeepNeuralNetworksintheCloud” by Zeng et al. presents a unified virtualization framework for general-purpose deep neural networks in the cloud, enabling multi-tenant sharing for both the Convolution Neural Network (CNN) and the Recurrent Neural Network (RNN) accelerators on a single FPGA. Finally, the paper “ ScalablePhylogenyReconstructionwithDisaggregatedNear-memoryProcessing” by Alachiotis et al. explores the potential of deploying custom acceleration units adjacently to disaggregated-memory controller on memory bricks (in IBM dReDBox terminology), which is implemented on FPGA technology, to reduce data movement and improve performance and energy efficiency when reconstructing large phylogenies (evolutionary relationships among organisms).
We would like to thank all the authors for submitting their work and the anonymous reviewers for their careful evaluation and thoughtful reviews in selecting these manuscripts for publication. We also would like to thank Deming Chen (Editor in Chief, ACM TRETS) and Megan Shuler (Editorial Associate, ACM TRETS) for their support throughout the review process. We hope you enjoy this Special Issue.
Ken Eguro, Microsoft
email: eguro@microsoft.
Stephen Neuendorffer, AMD/Xilinx
email: stephenn@amd.
Viktor Prasanna, University of Southern California
email: prasanna@usc.
Hongbo Rong, Intel
email: hongbo.
Guest Editors
Index Terms
- Introduction to Special Issue on FPGAs in Data Centers, Part II
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