Abstract
Read disturb is a circuit-level noise in flash-based Solid-State Drives (SSDs), induced by intensive read requests, which may result in unexpected read errors. The approach of read refresh (RR) is commonly adopted to mitigate its negative effects by unconditionally migrating all valid data pages in the RR block to another new block. However, routine RR operations greatly impact the I/O responsiveness of SSDs, because the processing on normal I/O requests must be blocked at the same time. To further reduce the negative effects of read refresh, this article proposes a read refresh scheduling and data reallocation method to deal with two primary issues with respect to an RR operation, including where to place data pages and when to trigger page migrations. Specifically, we first construct a data reallocation model to match the data pages in the RR block and the destination blocks for addressing the issue of where to place the data. The model considers not only the read hotness of pages in the RR block, but also the accumulated read counts of the destination blocks. Moreover, for addressing the issue of when to trigger data migrations, we build a timing decision model to determine the time points for completing page migrations by considering the factors of the intensity of I/Os and the disturb situation on the RR block. Through a series of simulation experiments based on several realistic disk traces, we illustrate that the proposed RR scheduling and data reallocation mechanism can noticeably reduce the read errors by more than
- [1] B. Kim, J. Choi, and S. Min. 2019. Design tradeoffs for SSD reliability. In FAST. Google ScholarDigital Library
- [2] S. Aritome. 2015. NAND Flash Memory Technologies. John Wiley & Sons.Google Scholar
- [3] Y. Luo, S. Ghose, Y. Cai, et al. 2018. Improving 3D NAND flash memory lifetime by tolerating early retention loss and process variation. In Proceedings of the ACM on Measurement and Analysis of Computing Systems.
DOI: https://doi.org/10.1145/3224432 Google ScholarDigital Library - [4] Y. Cai, O. Mutlu, E. F. Haratsch, et al. 2013. Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation. In ICCD.Google Scholar
- [5] K. Ha, J. Jeong, and J. Kim. 2015. An integrated approach for managing read disturbs in high-density NAND flash memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
DOI: https://doi.org/10.1109/TCAD.2015.2504868 Google ScholarDigital Library - [6] Y. Cai, Y. Luo, S. Ghose, et al. 2018. Read disturb errors in MLC NAND flash memory. arXiv preprint arXiv:1805.03283.Google Scholar
- [7] L. Grupp, J. Davis, and S. Swanson. 2012. The bleak future of NAND flash memory. In FAST. Google ScholarDigital Library
- [8] Y. Deguchi, T. Tokutomi, and K. Takeuchi. 2016. System-level error correction by read-disturb error model of 1Xnm TLC NAND flash memory for read-intensive enterprise solid-state drives (SSDs). In IRPS.Google Scholar
- [9] A. Kobayashi, H. Watanabe, Y. Sakaki, et al. 2017. Investigate of read disturb error in 1Ynm NAND flash memories for system level solution. In IRPS.Google Scholar
- [10] H. Watanabe, Y. Deguchi, A. Kobayashi, et al. 2018. System-level read disturb suppression techniques of TLC NAND flash memories for read-hot/cold data mixed applications. Solid-State Electron.
DOI: https://doi.org/10.1016/j.sse.2018.05.004Google Scholar - [11] P. Desnoyers. 2010. Empirical evaluation of NAND flash memory performance. ACM SIGOPS Oper. Syst. Review.
DOI: https://doi.org/10.1145/1740390.1740402 Google ScholarDigital Library - [12] Micron Technical Note (No. TN-29-27): Design and Use Considerations for NAND Flash Memory. Retrieved from https://media-www.micron.com/-/media/client/global/documents/products/technical-note/nand-flash/tn2917.pdf.Google Scholar
- [13] E. Xu, M. Zheng, F. Qin, et al. 2019. Lessons and actions: What we learned from 10K SSD-related storage system failures. In ATC. Google ScholarDigital Library
- [14] C. Manning. 2012. Yaffs NAND Flash Failure Mitigation. Retrieved from https://yaffs.net/sites/default/files/downloads/YaffsNandFailureMitigation.pdf.Google Scholar
- [15] W. Liu, F. Wu, M. Zhang, et al. 2019. Characterizing the reliability and threshold voltage shifting of 3D charge trap NAND flash. In DATE.Google Scholar
- [16] J. Li, B. Huang, Z. Sha, et al. 2020. Mitigating negative impacts of read disturb in SSDs. In ACM Transactions on Design Automation of Electronic Systems.
DOI: https://doi.org/10.1145/3410332 Google ScholarDigital Library - [17] Y. Pan, G. Dong, Q. Wu, et al. 2012. Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications. In HPCA. Google ScholarDigital Library
- [18] Y. Cai, Y. Luo, S. Ghose, et al. 2015. Read disturb errors in MLC NAND flash memory: Characterization, mitigation, and recovery. In DSN. Google ScholarDigital Library
- [19] T. Wu, Y. Ma, and L. Chang. 2018. Flash read disturb management using adaptive cell bit-density with in-place reprogramming. In DATE.Google Scholar
- [20] C. Liu, Y. Chang, and Y. Chang. 2015. Read leveling for flash storage systems. In SYSTOR. Google ScholarDigital Library
- [21] O. Mutlu. 2017. The RowHammer problem and other issues we may face as memory becomes denser. In DATE. Google ScholarDigital Library
- [22] Y. Cai, G. Yalcin, O. Mutlu, et al. 2012. Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. In ICCD.Google Scholar
- [23] J. Guo, Z. Chen, D. Wang, et al. 2014. DPA: A data pattern aware error prevention technique for NAND flash lifetime extension. In ASP-DAC.Google Scholar
- [24] J. Werner, E. Cohen, and T. Canepa. 2014. Read disturb handling for non-volatile solid state media. U.S. Patent Application 13/729,966.Google Scholar
- [25] Y. Seo, J. Yun, W. Lee, et al. 2013. Memory controller, method of operating the same and memory system including the same, U.S. Patent 14/081 371.Google Scholar
- [26] B. Huang, J. Liao, J. Li, et al. 2020. Read disturb-aware write scheduling and data reallocation in SSDs. In IEICE Electronics Express.
DOI: https://doi.org/10.1587/elex.17.20200015Google Scholar - [27] M. Zhao, J. Li, Z. Cai, et al. 2021. Block attribute-aware data reallocation to alleviate read disturb in SSDs. In DATE.Google Scholar
- [28] D. Bertsekas. Nonlinear Programming (3rd ed.). Athena Scientific.Google Scholar
- [29] Y. Hu, H. Jiang, D. Feng, et al. 2013. Exploring and exploiting the multilevel parallelism inside SSDs for improved performance and endurance. In IEEE TC.
DOI: https://doi.org/10.1109/TC.2012.60 Google ScholarDigital Library - [30] W. Zhang, Q. Cao, H. Jiang, et al. 2018. PA-SSD: A page-type aware TLC SSD for improved write/read performance and storage efficiency. In ICS. Google ScholarDigital Library
- [31] K. Zhao, W. Zhao, H. Sun, et al. 2013. LDPC-in-SSD: Making advanced error correction codes work effectively in solid state drives. In FAST. Google ScholarDigital Library
- [32] Y. Du, Y. Zhou, M. Zhang, et al. 2019. Adapting layer RBERs variations of 3D flash memories via multi-granularity progressive LDPC reading. In DAC. Google ScholarDigital Library
- [33] J. Cui, Y. Zhang, L. Shi, et al. 2020. Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems. Journal of Systems Architecture.
DOI: https://doi.org/10.1016/j.sysarc.2019.101685Google Scholar - [34] Search Engine I/O. Retrieved from http://traces.cs.umass.edu/index.php/Storage/Storage.Google Scholar
- [35] Microsoft Production Server Traces. Retrieved from http://iotta.snia.org/traces/158.Google Scholar
- [36] D. Narayanan, A. Donnelly, and A. Rowstron. 2008. Write off-loading: Practical power management for enterprise storage. ACM Transactions on Storage.
DOI: https://doi.org/10.1145/1416944.1416949 Google ScholarDigital Library - [37] G. Yadgar, M. Gabel, S. Jaffer, et al. 2021. SSD-based workload characteristics and their performance implications. ACM Transactions on Storage.
DOI: https://doi.org/10.1145/3423137 Google ScholarDigital Library - [38] YCSB RocksDB SSD Traces. 2020. Retrieved from http://iotta.snia.org/traces/28568.Google Scholar
- [39] Y. Chang, J. Hsieh, and T. Kuo. 2010. Improving flash wear leveling by proactively moving static data. In IEEE Transactions on Computers.
DOI: https://doi.org/10.1109/TC.2009.134 Google ScholarDigital Library - [40] C. Lee, T. Kumano, T. Matsuki, et al. 2017. Understanding storage traffic characteristics on enterprise virtual desktop infrastructure. In SYSTOR.Google Scholar
Index Terms
- Read Refresh Scheduling and Data Reallocation against Read Disturb in SSDs
Recommendations
Mitigating Negative Impacts of Read Disturb in SSDs
Read disturb is a circuit-level noise in solid-state drives (SSDs), which may corrupt existing data in SSD blocks and then cause high read error rate and longer read latency. The approach of read refresh is commonly used to avoid read disturb errors by ...
Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery
DSN '15: Proceedings of the 2015 45th Annual IEEE/IFIP International Conference on Dependable Systems and NetworksNAND flash memory reliability continues to degrade as the memory is scaled down and more bits are programmed per cell. A key contributor to this reduced reliability is read disturb, where a read to one row of cells impacts the threshold voltages of ...
Exploiting Refresh Effect of DRAM Read Operations: A Practical Approach to Low-Power Refresh
Dynamic random access memory (DRAM) requires periodic refresh operations to retain its data. In practice, DRAM retention times are normally distributed from 64 ms to several seconds. However, the conventional refresh method uses 64 ms as the refresh ...
Comments