research-article

A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks

Authors:

Zibin DaiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 27, Issue 4

Article No.: 36, Pages 1 - 13

https://doi.org/10.1145/3498339

Published: 24 May 2022 Publication History

Abstract

Side-channel attack (SCA) reveals confidential information by statistically analyzing physical manifestations, which is the serious threat to cryptographic circuits. Various SCA circuit-level countermeasures have been proposed as fundamental solutions to reduce the side-channel vulnerabilities of cryptographic implementations; however, such approaches introduce non-negligible power and area overheads. Among all of the circuit components, flip-flops are the main source of information leakage. This article proposes a three-phase single-rail pulse register (TSPR) based on the three-independent-gate field effect transistor (TIGFET) to achieve all desired properties with improved metrics of area and security. TIGFET-based TSPR consumes a constant power (MCV is 0.25%), has a low delay (12 ps), and employs only 10 TIGFET devices, which is applicable for the low-overhead and high-security cryptographic circuit design compared to the existing flip-flops. In addition, a set of TIGFET-based combinational basic gates are designed to reduce the area occupation and power consumption as much as possible. As a proof of concept, a simplified advanced encryption algorithm (AES), SM4 block cipher algorithm (SM4), and light-weight cryptographic algorithm (PRESENT) are built with the TIGFET-based library. SCA is implemented on the cryptographic implementations to prove its SCA resilience, and the SCA results show that the correct key of cryptographic circuits with TIGFET-based TSPRs is not guessed within 2,000 power traces.

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Cited By

Qi HLiu H(2024)Low Power Application Design of Adaptive Circuits Based on Deep Learning Algorithm2024 Asia-Pacific Conference on Software Engineering, Social Network Analysis and Intelligent Computing (SSAIC)10.1109/SSAIC61213.2024.00178(882-886)Online publication date: 10-Jan-2024
https://doi.org/10.1109/SSAIC61213.2024.00178
Afrin FTabil Ahammed MHossain S(2022)Implementation of CMOS Logic Gates Using ASiNR-based TFET2022 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering (WIECON-ECE)10.1109/WIECON-ECE57977.2022.10150661(342-345)Online publication date: 30-Dec-2022
https://doi.org/10.1109/WIECON-ECE57977.2022.10150661

Index Terms

A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks
1. Security and privacy

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 27, Issue 4

July 2022

275 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3517032

Editor:
X. Sharon Hu
University of Notre Dame, USA

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 24 May 2022

Accepted: 01 November 2021

Revised: 01 September 2021

Received: 01 July 2021

Published in TODAES Volume 27, Issue 4

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Cited By

Qi HLiu H(2024)Low Power Application Design of Adaptive Circuits Based on Deep Learning Algorithm2024 Asia-Pacific Conference on Software Engineering, Social Network Analysis and Intelligent Computing (SSAIC)10.1109/SSAIC61213.2024.00178(882-886)Online publication date: 10-Jan-2024
https://doi.org/10.1109/SSAIC61213.2024.00178
Afrin FTabil Ahammed MHossain S(2022)Implementation of CMOS Logic Gates Using ASiNR-based TFET2022 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering (WIECON-ECE)10.1109/WIECON-ECE57977.2022.10150661(342-345)Online publication date: 30-Dec-2022
https://doi.org/10.1109/WIECON-ECE57977.2022.10150661

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