Shunjun Qian
ABSTRACT
This paper proposes a low-latency multi-layer pipelined hardware implementation scheme of context based adaptive binary arithmetic coding (CABAC) for H.265/HEVC, which improves the coding performance and reduces the encoding latency with less hardware overhead. It is verified, debugged and optimized on the FPGA hardware platform. From the synthesis results on Xilinx K7 series FPGA, it can be seen that at 200MHz clock, the CABAC encoding of this scheme only uses 12K LUT resources, supports 1080P60Hz video encoding, and the encoding latency is as low as 6.7us. Experiments and calculations show that the proposed scheme can complete 8K UHD real-time video encoding using 59.71K logic gates at 800MHz clock on ASIC chip.
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Index Terms
- A Pipelined Multi-Tiered Hardware Acceleration Approach Towards Content Addressable Binary Arithmetic
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