Yendo Hu
ABSTRACT
Video latency plays a critical role in applications that require real time delivery of video content. Key areas include video teleconferencing, remote control, cloud gaming, and live news gathering. Given the value latency plays into these markets, video latency measurement remains an important topic. With the advent of artificial intelligence and deep learning neural networks, reliable low latency transmission becomes critical for automated real time control. Human judgements and one-off manual procedures are no longer reliable. Frame freezes, frame jumps, slow clock drifts, or even frame level corruption can bring instability into the tight control loop, resulting in jitter, drifts, and noise to the remotely controlled target. There exist several classes of video latency measurement approaches, including watermark embedding, out-of-band metadata, and passive feature extraction. In addressing the integrity monitoring of latency for the existing video delivery network base, this paper presents a novel approach following the passive feature extraction class. The solution extracts unique characteristics within each frame of the video stream in question. The characteristics must be unique between frames in the stream, within the range of the maximum delay window. The same feature extraction method is then applied to the delayed stream. By comparing the features between any two frames, the measurement can be carried out by finding the best match between the two streams. The proposal was implemented on an Xilinx Artix family FPGA, utilizing only 20KLUTS of resources. Given the memory size required to store the reference frames, external DDR memory is necessary to support 8K video formats.
- Jamalzadeh, M., L.-D. Ong, and M.N.B.M. Nor, 5G Technologies: A New Network Architectures and Design. Journal of Internet Technology, 2018. 19(7): p. 1983--1991Google Scholar
- Du, G.M., et al., A low-latency DMM-1 encoder for 3D-HEVC. Journal of Real-Time Image Processing, 2020. 17(3): p. 691--702.Google ScholarDigital Library
- Hwang, S., et al., High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems. Electronics, 2019. 8(7).Google Scholar
- 3GPP 26.929: QoE parameters and metrics relevant to the Virtual Reality (VR) user experience, https://www.3gpp.org/ftp/Specs/archive/26_series/26.929/.Google Scholar
- Ruan, J.J. and D.L. Xie, Networked VR: State of the Art, Solutions, and Challenges. Electronics, 2021. 10(2): p. 18.Google Scholar
- El Marai, O. and T. Taleb, Smooth and Low Latency Video Streaming for Autonomous Cars During Handover. Ieee Network, 2020. 34(6): p. 302--309.Google ScholarDigital Library
- ITU-R BT.1120-6, Digital interfaces for HDTV studio signalsGoogle Scholar
- SJ/T 11407.1-2009, Content protection specifications for digital interface - Part 1: System architectureGoogle Scholar
- GB/T 19263--2003, Technical specification of transport of MPEG-2 signals in SDH networkGoogle Scholar
- Minallah Nasru, Ullah Khadem, Frnda Jaroslav, et al. On the Performance of Video Resolution, Motion and Dynamism in Transmission Using Near-Capacity Transceiver for Wireless Communication[J]. Entropy, 2021, 23(5):562--562.Google ScholarCross Ref
Index Terms
- An FPGA Implementation for Non-Evasive Video Latency Measurement
Recommendations
Low-latency modular packet header parser for FPGA
ANCS '12: Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systemsPacket parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very ...
Measurement of ATM frame latency
CompSysTech '03: Proceedings of the 4th international conference conference on Computer systems and technologies: e-LearningThis paper addresses the problem of measuring frame latency in ATM switches. The frames consisting of several ATM cells may arrive with numerous gaps between cells. It is important that the gaps present in the input stream be not counted towards the ...
The Design and Implementation of a Latency-Aware Packet Classification for OpenFlow Protocol based on FPGA
ICNCC '18: Proceedings of the 2018 VII International Conference on Network, Communication and ComputingPacket classification has been recognized as one of the most significant functions in contemporary network infrastructures. Furthermore, a number of modern applications such as IoTs contain very strict constraints on the latency of network ...
Comments