Necati Uysal
Abstract
Modern digital circuits are often required to operate in multiple modes to cater to variable frequency and power requirements. Consequently, the clock networks for such circuits must be synthesized, meeting different timing constraints in different operational modes. The overall power consumption and robustness to variations of a clock network are determined by the topology. However, state-of-the-art clock networks use the same topology in every mode, despite that timing constraints in low- and high-performance modes can be very different. In this article, we propose a clock network with a mode-reconfigurable topology (MRT) for circuits with positive-edge-triggered sequential elements. In high-performance modes, the MRT structure is reconfigured into a near-tree to provide the required robustness to variations. In low-performance modes, the MRT structure is reconfigured into a tree to save power. Non-tree (or near-tree) structures provide robustness to variations by appropriately constructing multiple alternative paths from the clock source to the clock sinks, which neutralizes the negative impact of variations. In MRT structures, OR-gates are used to join multiple alternative paths into a single path. Hence, the MRT structures consume no short-circuit power because there is only one gate driving each net. Moreover, it is straightforward to reconfigure an MRT structure into a tree topology using a single clock gate. In high-performance modes, the experimental results demonstrate that MRT structures have \( 25\% \) lower power consumption than state-of-the-art near-tree structures. In low-performance modes, the power consumption of the MRT structure is similar to the power consumption of a clock tree.
- [1] . 2003. Statistical timing analysis for intra-die process variations with spatial correlations. In Proceedings of the International Conference on Computer Aided Design (IEEE Cat. No.03CH37486). 900–907.Google Scholar
Cross Ref
- [2] . 1992. Zero-skew clock routing trees with minimum wirelength. In Proceedings of the IEEE International ASIC Conference and Exhibit. 17–21.Google ScholarCross Ref
- [3] . 2011. Synthesis of low power clock trees for handling power-supply variations. In Proceedings of the International Symposium on Physical Design (ISPD’11). 37–44.Google ScholarDigital Library
- [4] . 1992. Zero skew clock net routing. In Proceedings of the Design Automation Conference (DAC). 518–523.Google ScholarCross Ref
- [5] . 1996. An algorithm for zero-skew clock tree routing with buffer insertion. In Proceedings of the European Conference on Design and Test (EDTC’96). 230.Google ScholarCross Ref
- [6] . 1993. A clustering-based optimization algorithm in zero-skew routings. In Proceedings of the Design Automation Conference (DAC). 612–616.Google ScholarDigital Library
- [7] . 2015. Construction of reconfigurable clock trees for MCMM designs. In Proceedings of the Design Automation Conference (DAC). 1–6.Google ScholarDigital Library
- [8] . 2017. Benchmark Circuits for Clock Scheduling and Synthesis. (Version 3.0). Purdue University Research Repository.
DOI: Google ScholarCross Ref - [9] . 2015. Cost-effective robustness in clock networks using near-tree structures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 4 (2015), 515–528.Google ScholarDigital Library
- [10] . 1990. Clock skew optimization. IEEE Trans. Comput. 39, 7 (1990), 945–951.Google ScholarDigital Library
- [11] . 2003. Clock scheduling and clocktree construction for high performance ASICs. In Proceedings of the International Conference on Computer Aided Design (IEEE Cat. No.03CH37486) (ICCAD). 232–239.Google ScholarCross Ref
- [12] . 2011. Multilevel tree fusion for robust clock networks. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). 632–639.Google ScholarDigital Library
- [13] . 2009. Post-CTS clock skew scheduling with limited delay buffering. In Proceedings of the International Midwest Symposium on Circuits and Systems (MWSCAS). 224–227.Google ScholarCross Ref
- [14] . 2011. Cross link insertion for improving tolerance to variations in clock network synthesis. In Proceedings of the International Symposium on Physical Design (ISPD). 29–36.Google ScholarDigital Library
- [15] . [n. d.]. [Available Online] http://ngspice.sourceforge.net/.Google Scholar
- [16] . 2004. Reducing clock skew variability via cross links. In Proceedings of the Design Automation Conference, 2004. (DAC). 18–23.Google ScholarDigital Library
- [17] . 2005. Improved algorithms for link-based non-tree clock networks for skew variability reduction. In Proceedings of the International Symposium on Physical Design (ISPD). 55–62.Google ScholarDigital Library
- [18] . 2015. Clock tree resynthesis for multi-corner multi-mode timing closure. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 4 (2015), 589–602.Google ScholarDigital Library
- [19] . 2015. Synthesis for power-aware clock spines. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). 126–131.Google ScholarDigital Library
- [20] . 2010. High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). 452–457.Google ScholarDigital Library
- [21] . 2002. Energy-delay tradeoffs in combinational logic using gate sizing and supply voltage optimization. In Proceedings of the European Solid-State Circuits Conference. 211–214.Google Scholar
- [22] . 2010. ISPD 2010 high performance clock network synthesis contest: Benchmark suite and results. In Proceedings of the International Symposium on Physical Design (ISPD). 143.Google ScholarDigital Library
- [23] . 2009. ISPD 2009 clock network synthesis contest. In Proceedings of the International Symposium on Physical Design (ISPD). 149–150.Google Scholar
- [24] . 2002. UST/DME: A clock tree router for general skew constraints. ACM Trans. Des. Autom. Electron. Syst. 7, 3 (2002), 359–379.Google ScholarDigital Library
- [25] . 1991. Exact zero skew. In Proceedings of the International Conference on Computer-Aided Design Digest of Technical Papers. 336–339.Google ScholarCross Ref
- [26] . 2020. Synthesis of clock networks with a mode reconfigurable topology and no short circuit current. In Proceedings of the International Symposium on Physical Design (ISPD). 103–110.Google ScholarDigital Library
- [27] . 2006. Combinatorial algorithms for fast clock mesh optimization. In Proceedings of the International Conference on Computer Aided Design (ICCAD). 563–567.Google Scholar
- [28] . 2005. Practical techniques to reduce skew and its variations in buffered clock networks. In Proceedings of the International Conference on Computer-Aided Design. (ICCAD). 592–596.Google ScholarCross Ref
- [29] . 2009. Electronic Design Automation: Synthesis, Verification, and Test. Morgan-Kaufmann Publishers, Inc., San Francisco, CA.Google Scholar
- [30] . 2010. Local clock skew minimization using blockage-aware mixed tree-mesh clock network. In Proceedings of the International Conference on Computer-Aided Design (ICCAD). 458–462.Google ScholarDigital Library
Index Terms
- Synthesis of Clock Networks with a Mode-Reconfigurable Topology
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