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Juxtaposing Vivado Design Flows in Batch Mode

Published: 22 February 2022 Publication History

Abstract

Re-configurable hardware devices are at the forefront of technological advancement and academic research, with their most prominent delegate being Field Programmable Gate Arrays (FPGAs). A typical FPGA design cycle may consist of multiple runs considering each available option targeting conflicting quality-of-result characteristics, based on a set of constraints, that narrows down the number of feasible implementations. Thus, prior knowledge of each strategy’s performance might be considered rather useful from a designer’s perspective. This paper presents a comparative study considering all available synthesis and implementation strategies of Xilinx’s Vivado Design Suite, and tries to pinpoint key characteristics that may be effective in view of future endeavors.

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    PCI '21: Proceedings of the 25th Pan-Hellenic Conference on Informatics
    November 2021
    499 pages
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    Published: 22 February 2022

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    Author Tags

    1. implementation
    2. placement
    3. routing
    4. synthesis

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    Overall Acceptance Rate 190 of 390 submissions, 49%

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