Xiang Gao
ABSTRACT
Modern very large-scale integration (VLSI) designs typically use a lot of macros (RAM, ROM, IP) that occupy a large portion of the core area. Also, macro placement being an early stage of the physical design flow, followed by standard cell placement, physical synthesis (place-opt), clock tree synthesis and routing, etc., has a big impact on the final quality of result (QoR). There is a need for Electronic Design Automation (EDA) physical design tools to provide predictions for congestion, timing, and power etc., with certainty for different macro placements before running time-consuming flows. However, the diversity of IC designs that commercial EDA tools must support and the limited number of similar designs that can provide training data, make such machine learning (ML) predictions extremely hard. Because of this, ML models usually need to be completely retrained for unseen designs to work properly. However, collecting full flow macro placement ML data is time consuming and impractical. To make things worse, common ML methods, such as regression, support vector machine (SVM), random forest (RF), neural network (NN) in general, lack a good estimation of prediction accuracy or confidence and lack debuggability for cross-design applications. In this paper, we present a novel discerning ensemble technique for cross-design ML prediction for macro placement. We developed our solution based on a large number of designs with different design styles and technology nodes, and tested the solution on 8 leading-edge industry designs and achieved comparable or even better results in a few hours (per design) than manual placement results that take many engineers weeks or even months to achieve. Our method shows great promise for many ML problems in EDA applications, or even in other areas.
- I. L. Markov, J. Hu, and M. Kim, "Progress and Challenges in VLSI Placement Research", Proc. of the IEEE, 103(11) (2015), pp. 1985--2003Google Scholar
Cross Ref
- A. B. Kahng. 2018. Machine Learning Applications in Physical Design: Recent Results and Directions. In ISPD'18: 2018 International Symposium on Physical Design, March 25--28, 2018, Monterey, CA, USA. ACM, New York, NY, USA, 6 pages. https://doi.org/10.1145/3177540.3177554Google Scholar
- A. B. Kahng, UCSD Depts. of CSE and ECE, La Jolla, CA 92093-0404 USA, [email protected] https://vlsicad.ucsd.edu/?abk/. 2021. Advancing Placement. In Proceedings of the 2021 International Symposium on Physical Design (ISPD '21), March 22--24, 2021, Virtual Event, USA. ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/3439706.3446884Google Scholar
- G. Huang, J. Hu, Y. He, J. Liu, M. Ma, Z. Shen, J. Wu, Y. Xu, H. Zhang, K. Zhong, X. Ning, Y. Ma, H. Yang, B. Yu, H. Yang, and Y. Wang. 2021. Machine Learning for Electronic Design Automation: A Survey. 1, 1 (March 2021), 44 pagesGoogle Scholar
- Y. Lin, Z. Jiang, J. Gu, W. Li, S. Dhar, H. Ren, B. Khailany, and D. Z. Pan, "Dreamplace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement," IEEE TCAD, pp. 1--1, 2020.Google Scholar
- K. Jeong and A. B. Kahng, "Methodology from Chaos in IC Implementation", Proc. ISQED, 2010, pp. 885--892.Google Scholar
- A. B. Kahng and S. Mantik, "Measurement of Inherent Noise in EDA Tools", Proc. ISQED, 2002, pp. 206--211.Google ScholarDigital Library
- K. Jeong, A. B. Kahng, B. Lin, and K. Samadi. 2010. Accurate Machine-Learning-Based On-Chip Router Modeling. IEEE Embedded Systems Letters (ESL) 2, 3 (2010), 62--66.Google ScholarDigital Library
- W.-T. J. Chan, Y. D., A. B. Kahng, S. Nath, and K. Samadi. 2016. BEOL Stack-Aware Routability Prediction from Placement Using Data Mining Techniques. In IEEE International Conference on Computer Design (ICCD). 41--48.Google Scholar
- W.-K. Cheng, Y.-Y. Guo, and C.-S. Wu, "Evaluation of Routability-driven Macro Placement with Machine-Learning Technique", The 7th IEEE International Symposium on Next-Generation Electronics (ISNE 2018)Google Scholar
- Y. Huang, Z. Xie, G.-Q. Fang, T.-C. Yu, H. Ren, S.-Y. Fang, Y. Chen, and J. Hu, "Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model," 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, pp. 180--185, doi: 10.23919/DATE.2019.8715126.Google Scholar
- A. Goldie and A. Mirhoseini. 2020. Placement Optimization with Deep Reinforcement Learning. In Proceedings of the 2020 International Symposium on Physical Design (ISPD '20), March 29-April 1, 2020, Taipei, Taiwan. ACM, New York, NY, USA, 5 pages. https://doi.org/10.1145/3372780.3378174Google ScholarDigital Library
- A. Mirhoseini, A. Goldie, M. Yazgan, J. Jiang, E. M. Songhori, S. Wang, Y.-J. Lee, E. Johnson, O. Pathak, S. Bae, A. Nazi, J. Pak, A. Tong, K. Srinivasa, W. Hang, E. Tuncer, A. Babu, Quoc V. Le, J. Laudon, R. C. Ho, R. Carpenter, and J. Dean. 2020. Chip Placement with Deep Reinforcement Learning. CoRR abs/2004.10746 (2020). arXiv:2004.10746Google Scholar
- Z. Jiang, E. Songhori, S. Wang, A. Goldie, A. Mirhoseini, J. Jiang, Y.J. Lee, and D. Pan, 2021. Delving into Macro Placement with Reinforcement Learning. 1--3. 10.1109/MLCAD52597.2021.9531313.Google Scholar
- S. I. Ward, D. Ding, and D. Z. Pan. 2012. PADE: A High-Performance Placer with Automatic Datapath Extraction and Evaluation Through High Dimensional Data Learning. In ACM/IEEE Design Automation Conference (DAC). 756--761.Google Scholar
- S. I. Ward, M-C Kim, N. Viswanathan, Z. Li, C. J. Alpert, E. E. Swartzlander Jr., and D. Z. Pan. 2012. Keep it Straight: Teaching Placement How to Better Handle Designs with Datapaths. In ACM International Symposium on Physical Design (ISPD). 79--86.Google Scholar
- D. Vashisht, H. Rampal, H. Liao, Y. Lu, D. Shanbhag, E. Fallon, and L.B. Kara. 2020. Placement in Integrated Circuits using Cyclic Reinforcement Learning and Simulated Annealing, arXiv:2011.07577v1 [cs.AI] 15 Nov 2020Google Scholar
- Y.-C. Lu, S. Pentapati, and S. K. Lim. 2021. The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks. In Proceedings of the 2021 International Symposium on Physical Design (ISPD '21), March 22--24, 2021, Virtual Event, USA. ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/3439706.3447045Google ScholarDigital Library
- W-T J. Chan, P-H Ho, A. B. Kahng, and P. Saxena. 2017. Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning. In Proceedings of the 2017 ACM on International Symposium on Physical Design (ISPD '17). Association for Computing Machinery, New York, NY, USA, 15--21. https://doi.org/10.1145/3036669.3036681Google Scholar
- A. F. Tabrizi, N.K. Rakai, Darav, S. Xu, L. Rakai, I. Bustany, A. Kennings, and L. Behjat. "A Machine Learning Framework to Identify Detailed Routing Short Violations from a Placed Netlist." 2018 55th ACM/ESDA/IEEE Design Automation Conference (2018): 1--6.Google Scholar
- P. Spindler and F. M. Johannes., 2007. Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement. In Design, Automation & Test in Europe Conference & Exhibition (DATE).Google ScholarDigital Library
- Z. Xie, Y-H Huang, G-Q Fang, H. Ren, S-Y Fang, Y. Chen, and J. Hu. 2018. RouteNet: Routability Prediction for Mixed-Size Designs Using Convolutional Neural Network. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 80.Google Scholar
- Z. Xie, H. Ren, B. Khailany, Y. Sheng, S. Santosh, J. Hu, and Y. Chen. 2020. PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. In IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC). 13--18.Google Scholar
- R. Liang, H. Xiang, D. Pandey, L. N. Reddy, S. Ramji, G-J Nam, and J. Hu. 2020. DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network. In ACM International Symposium on Physical Design (ISPD). 135--142.Google Scholar
- R. Liang, Z. Xie, J. Jung, V. Chauha, Y. Chen, J. Hu, H. Xiang, and G. J. Nam. 2020. Routing-Free Crosstalk Prediction. In 2020 IEEE/ACM International Conference on Computer Aided Design (ICCAD). 1--9.Google Scholar
- T-C Yu, S-Y Fang, H-S Chiu, K-S Hu, P. H-Y Tai, C. C-F Shen, and H. Sheng. 2020. Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning. In Proceedings of the 2020 International Symposium on Physical Design (ISPD '20). Association for Computing Machinery, New York, NY, USA, 65--72. https://doi.org/10.1145/3372780.3375562Google Scholar
- J. Chen, J. Kuang, G. Zhao, D. J. -H. Huang and E. F. Y. Young, "PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning," 2020 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2020, pp. 1--8.Google Scholar
- L. Li, Y. Cai and Q. Zhou, "An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1--5, doi: 10.1109/ISCAS51556.2021.9401274.Google Scholar
- D. H. Wolpert, (1992). Stacked generalization. Neural networks, 5(2), 241--259.Google Scholar
- M. P. Perrone and L. N. Cooper, 1992. When networks disagree: Ensemble methods for hybrid neural networks: BROWN UNIV PROVIDENCE RI INST FOR BRAIN AND NEURAL SYSTEMS.Google Scholar
- L. Breiman, (1996a). Bagging predictors. Machine learning, 24(2), 123--140.Google Scholar
- Y. Freund, (1995). Boosting a weak learning algorithm by majority. Information and computation, 121(2), 256--285Google Scholar
- T. Hastie, R. Tibshirani, and J. Friedman, 2009. "The Elements of Statistical learning: Data Mining, Inference and Prediction" 2nd Edition, Springer ScienceGoogle Scholar
- T. Chen and C. Guestrin. 2016. XGboost: A scalable tree boosting system. In ACM International Conference on Knowledge Discovery and Data Mining (DMKD). 785--794.Google Scholar
- W. Hamilton, Z. Ying, and J. Leskovec. 2017. Inductive representation learning on large graphs. In IEEE Conference and Workshop on Neural Information Processing Systems (NIPS). 1024--1034.Google Scholar
- M. Shahhosseini, G. Hu, and H. Pham, "Optimizing Ensemble Weights and Hyperparameters of Machine Learning Models for Regression Problems"Google Scholar
Index Terms
- Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble
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