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Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest

Published: 13 April 2022 Publication History

Abstract

Computer-aided design (CAD) tools mainly optimize for power, performance, and area (PPA). However, given a large number of serious hardware-security threats that are emerging, future CAD flows must also incorporate techniques for designing secure integrated circuits (ICs). In fact, the stakes are quite high for IC vendors and design companies, as security risks that are not addressed during design time will inevitably be exploited in the field, where vulnerabilities are almost impossible to fix. However, there is currently little to no experience related to designing secure ICs available within the CAD community. For the very first time, this contest seeks to actively engage with the community to close this gap. The theme of this contest is security closure of physical layouts, that is, hardening the physical layouts at design time against threats that are executed post-design time. More specifically, this contest is focused on selected and seminal threats that, once taken in, are relatively simple to approach and mitigate through means of physical design: Trojan insertion and probing as well as fault injection. Acting as security engineers, contest participants will iteratively and proactively evaluate and fix the vulnerabilities of provided benchmark layouts. Benchmarks and submissions are based on the generic DEF format and related files. Thus, participants are free to use any physical-design tools of their choice, helping us to open up the contest to the community at large.

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Cited By

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  • (2025)DEFending Integrated Circuit LayoutsIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.349281020(46-59)Online publication date: 1-Jan-2025
  • (2024)Beware Your Standard Cells! On Their Role in Static Power Side-Channel AttacksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339473643:12(4439-4452)Online publication date: Dec-2024
  • (2024)Rethinking IC Layout Vulnerability: Simulation-Based Hardware Trojan Threat Assessment with High Fidelity2024 IEEE Symposium on Security and Privacy (SP)10.1109/SP54263.2024.00160(3789-3804)Online publication date: 19-May-2024
  • Show More Cited By

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cover image ACM Conferences
ISPD '22: Proceedings of the 2022 International Symposium on Physical Design
April 2022
240 pages
ISBN:9781450392105
DOI:10.1145/3505170
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 13 April 2022

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Author Tags

  1. contest
  2. fault-injection attacks
  3. hardware security
  4. physical design
  5. probing attacks
  6. read-out attacks
  7. security closure
  8. trojans

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  • Research-article

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ISPD '22
Sponsor:
ISPD '22: International Symposium on Physical Design
March 27 - 30, 2022
Virtual Event, Canada

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

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ISPD '25
International Symposium on Physical Design
March 16 - 19, 2025
Austin , TX , USA

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Cited By

View all
  • (2025)DEFending Integrated Circuit LayoutsIEEE Transactions on Information Forensics and Security10.1109/TIFS.2024.349281020(46-59)Online publication date: 1-Jan-2025
  • (2024)Beware Your Standard Cells! On Their Role in Static Power Side-Channel AttacksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339473643:12(4439-4452)Online publication date: Dec-2024
  • (2024)Rethinking IC Layout Vulnerability: Simulation-Based Hardware Trojan Threat Assessment with High Fidelity2024 IEEE Symposium on Security and Privacy (SP)10.1109/SP54263.2024.00160(3789-3804)Online publication date: 19-May-2024
  • (2024)Safeguarding the Silicon: Strategies for Integrated Circuit Layout Protection2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS62602.2024.10808337(466-470)Online publication date: 7-Nov-2024
  • (2023)Benchmarking Advanced Security Closure of Physical LayoutsProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3578924(256-264)Online publication date: 26-Mar-2023
  • (2023)GDSII-Guard: ECO Anti-Trojan Optimization with Exploratory Timing-Security Trade-Offs2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247697(1-6)Online publication date: 9-Jul-2023
  • (2022)ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement LearningProceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security10.1145/3548606.3560690(1275-1289)Online publication date: 7-Nov-2022

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