research-article

The Future of FPGA Acceleration in Datacenters and the Cloud

Authors:

Christophe Bobda,

Joel Mandebi Mbongue,

Mohammad Ewais,

Juan Camilo Vega,

Suranga Handagala,

Martin Herbordt,

Hafsah Shahzad,

Burkhard Ringlein,

Ahmed Sanaullah,

Russell TessierAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 15, Issue 3

Article No.: 34, Pages 1 - 42

https://doi.org/10.1145/3506713

Published: 04 February 2022 Publication History

Abstract

In this article, we survey existing academic and commercial efforts to provide Field-Programmable Gate Array (FPGA) acceleration in datacenters and the cloud. The goal is a critical review of existing systems and a discussion of their evolution from single workstations with PCI-attached FPGAs in the early days of reconfigurable computing to the integration of FPGA farms in large-scale computing infrastructures. From the lessons learned, we discuss the future of FPGAs in datacenters and the cloud and assess the challenges likely to be encountered along the way. The article explores current architectures and discusses scalability and abstractions supported by operating systems, middleware, and virtualization. Hardware and software security becomes critical when infrastructure is shared among tenants with disparate backgrounds. We review the vulnerabilities of current systems and possible attack scenarios and discuss mitigation strategies, some of which impact FPGA architecture and technology. The viability of these architectures for popular applications is reviewed, with a particular focus on deep learning and scientific computing. This work draws from workshop discussions, panel sessions including the participation of experts in the reconfigurable computing field, and private discussions among these experts. These interactions have harmonized the terminology, taxonomy, and the important topics covered in this manuscript.

References

[1]

Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O’Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, et al. 2018. DLA: Compiler and FPGA overlay for neural network inference acceleration. In 28th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 411–4117.

[2]

A. Abdelsalam, F. Clad, C. Filsfils, S. Salsano, G. Siracusano, and L. Veltri. 2017. Implementation of virtual network function chaining through segment routing in a Linux-based NFV infrastructure. In IEEE Conference on Network Softwarization (NetSoft). 1–5. DOI:https://doi.org/10.1109/NETSOFT.2017.8004208

[3]

Francois Abel, Jagath Weerasinghe, Christoph Hagleitner, Beat Weiss, and Stephan Paredes. 2017. An FPGA platform for hyperscalers. In IEEE 25th Annual Symposium on High-Performance Interconnects. 29–32. DOI:https://doi.org/10.1109/HOTI.2017.13

[4]

Amran A. Al-Aghbari and Muhammad E. S. Elrabaa. 2019. Cloud-based FPGA custom computing machines for streaming applications. IEEE Access 7 (2019), 38009–38019.

[5]

Md Mahbub Alam, Shahin Tajik, Fatemeh Ganji, Mark Tehranipoor, and Domenic Forte. 2019. RAM-Jam: Remote temperature and voltage fault attack on FPGAs using memory collisions. In Workshop on Fault Diagnosis and Tolerance in Cryptography. 48–55.

[6]

Gustavo Alonso, Timothy Roscoe, David Cock, Muhsen Owaida, Kaan Kara, Dario Korolija, Zeke Wang, et al. 2020. Tackling hardware/software co-design from a database perspective. In 6th Biennial Conference on Innovative Data Systems Research (CIDR).

[7]

Amazon.com, Inc.2021. Amazon EC2 F1 Instances. Retrieved from https://aws.amazon.com/ec2/instance-types/f1/.

[8]

R. Amerson, R. J. Carter, W. B. Culbertson, P. Kuekes, and G. Snider. 1995. Teramac-configurable custom computing. In IEEE Symposium on FPGAs for Custom Computing Machines. 32–38.

Digital Library

[9]

ARM. 2010. AMBA 4 AXI4-Stream Protocol Specification. Technical Report. ARM.

[10]

ARM. 2011. AMBA AXI and ACE Protocol Specification. Technical Report. ARM.

[11]

Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, and Paolo Ienne. 2017. Virtualized execution runtime for FPGA accelerators in the cloud. IEEE Access 5 (2017), 1900–1910.

[12]

Daniel O. Awduche. 1999. MPLS and traffic engineering in IP networks. IEEE Commun. Mag. 37, 12 (1999), 42–47.

Digital Library

[13]

Hitesh Ballani, Paolo Costa, Thomas Karagiannis, and Ant Rowstron. 2011. Towards predictable datacenter networks. In ACM SIGCOMM Conference (SIGCOMM’11). Association for Computing Machinery, New York, NY, 242–253. DOI:https://doi.org/10.1145/2018436.2018465

Digital Library

[14]

R. Baxter, S. Booth, M. Bull, G. Cawood, J. Perry, M. Parsons, A. Simpson, A. Trew, A. McCormick, G. Smart, R. Smart, A. Cantle, R. Chamberlain, and G. Genest. 2007. Maxwell – A 64 FPGA supercomputer. In 2nd NASA/ESA Conference on Adaptive Hardware and Systems (AHS’07). 287–294. DOI:https://doi.org/10.1109/AHS.2007.71

Digital Library

[15]

Christian Beckhoff, Dirk Koch, and Jim Torresen. 2010. Short-circuits on FPGAs caused by partial runtime reconfiguration. In International Conference on Field Programmable Logic and Applications. 596–601.

Digital Library

[16]

D. Bernstein. 2014. Containers and cloud: From LXC to Docker to Kubernetes. IEEE Cloud Comput. 1, 3 (2014), 81–84.

[17]

Saman Biookaghazadeh, Pravin Kumar Ravi, and Ming Zhao. 2021. Toward multi-FPGA acceleration of the neural networks. ACM J. Emerg. Technol. Comput. Syst. 17, 2 (2021), 1–23.

Digital Library

[18]

Michaela Blott, Kimon Karras, Ling Liu, Kees Vissers, Jeremia Bär, and Zsolt István. 2013. Achieving 10Gbps line-rate key-value stores with FPGAs. In 5th USENIX Workshop on Hot Topics in Cloud Computing (HotCloud’13). USENIX Association, San Jose, CA. Retrieved from https://www.usenix.org/conference/hotcloud13/workshop-program/presentations/blott.

[19]

Michaela Blott, Ling Liu, Kimon Karras, and Kees Vissers. 2015. Scaling out to a single-node 80gbps memcached server with 40terabytes of memory. In 7th USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage’15). USENIX Association, Santa Clara, CA. Retrieved from https://www.usenix.org/conference/hotstorage15/workshop-program/presentation/blott.

Digital Library

[20]

Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O’Brien, Yaman Umuroglu, Miriam Leeser, and Kees Vissers. 2018. FINN-R: An end-to-end deep-learning framework for fast exploration of quantized neural networks. ACM Trans. Reconfig. Technol. Syst. 11, 3 (2018), 1–23.

Digital Library

[21]

Christophe Bobda. 2007. Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications (1st ed.). Springer Publishing Company, Incorporated.

Digital Library

[22]

C. Bobda, A. Majer, A. Ahmadinia, T. Haller, A. Linarth, and J. Teich. 2005. The Erlangen slot machine: Increasing flexibility in FPGA-based reconfigurable platforms. In IEEE International Conference on Field-Programmable Technology.37–42. DOI:https://doi.org/10.1109/FPT.2005.1568522

Digital Library

[23]

Marc Boulé and Zeljko Zilic. 2008. Automata-based assertion-checker synthesis of PSL properties. ACM Trans. Des. Autom. Electron. Syst. 13, 1 (Feb. 2008). DOI:https://doi.org/10.1145/1297666.1297670

Digital Library

[24]

Andrew Boutros, Eriko Nurvitadhi, Rui Ma, Sergey Gribok, Zhipeng Zhao, James C. Hoe, Vaughn Betz, and Martin Langhammer. 2020. Beyond peak performance: Comparing the real performance of AI-Optimized FPGAs and GPUs. In International Conference on Field-Programmable Technology (ICFPT). 10–19. DOI:https://doi.org/10.1109/ICFPT51103.2020.00011

[25]

Alexander Brant and Guy G. F. Lemieux. 2012. ZUMA: An open FPGA overlay architecture. In IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 93–96.

Digital Library

[26]

Stuart Byma, J. Gregory Steffan, Hadi Bannazadeh, Alberto Leon Garcia, and Paul Chow. 2014. FPGAs in the cloud: Booting virtualized hardware accelerators with openstack. In IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines. IEEE, 109–116.

Digital Library

[27]

A. M. Caulfield, E. S. Chung, A. Putnam, H. Angepat, Jeremy Fowers, Michael Haselman, Stephen Heil, Matt Humphrey, Puneet Kaur, Joo-Young Kim, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Lisa Woods, Sitaram Lanka, Derek Chiou, and Doug Burger. 2016. A cloud-scale acceleration architecture. In 49th IEEE/ACM International Symposium on Microarchitecture. 1–13.

Digital Library

[28]

Sai Rahul Chalamalasetti, Kevin Lim, Mitch Wright, Alvin Au Young, Parthasarathy Ranganathan, and Martin Margala. 2013. An FPGA memcached appliance. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays. 245–254.

Digital Library

[29]

Fei Chen, Yi Shan, Yu Zhang, Yu Wang, Hubertus Franke, Xiaotao Chang, and Kun Wang. 2014. Enabling FPGAs in the cloud. In 11th ACM Conference on Computing Frontiers. ACM, 3.

Digital Library

[30]

Xinyu Chen, Hongshi Tan, Yao Chen, Bingsheng He, Weng-Fai Wong, and Deming Chen. 2021. ThunderGP: HLS-based graph processing framework on FPGAs. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 69–80.

Digital Library

[31]

Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei, and Peng Wei. 2016. When Spark meets FPGAs: A case study for next-generation DNA sequencing acceleration. In 8th USENIX Workshop on Hot Topics in Cloud Computing (HotCloud’16).

Digital Library

[32]

Yuk-Ming Choi and Hayden Kwok-Hay So. 2014. Map-Reduce processing of k-means algorithm with FPGA-accelerated computer cluster. In IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors. 9–16.

[33]

Chung Eric, Fowers Jeremy, Ovtcharov Kalin, Papamichael Michael, Caulfield Adrian, Massengill Todd, Liu Ming, Lo Daniel, Alkalay Shlomi, and Haselman Michael. 2018. Serving DNNs in real time at datacenter scale with project brainwave. IEEE Micro 38, 2 (2018), 8–20.

[34]

Catalin Cimpano. 2020. Vast majority of cyber-attacks on cloud servers aim to mine cryptocurrency. Retrieved from https://www.zdnet.com/article/vast-majority-of-cyber-attacks-on-cloud-servers-aim-to-mine-cryptocurrency/.

[35]

Chris Conger, Ian Troxel, D. Espinoza, Vikas Aggarwal, and A. George. 2005. NARC: Network attached reconfigurable computing for high performance, network based applications. In 8th Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD’05).

[36]

Guohao Dai, Yi Shan, Fei Chen, Yu Wang, Kun Wang, and Huazhong Yang. 2014. Online scheduling for FPGA computation in the cloud. In International Conference on Field-Programmable Technology (FPT). IEEE, 330–333.

[37]

Tiziano De Matteis, Johannes de Fine Licht, Jakub Beránek, and Torsten Hoefler. 2019. Streaming message interface: High-performance distributed memory programming on reconfigurable hardware. In International Conference for High Performance Computing, Networking, Storage and Analysis. 1–33.

Digital Library

[38]

Javier Duarte, Philip Harris, Scott Hauck, Burt Holzman, Shih-Chieh Hsu, Sergo Jindariani, Suffian Khan, Benjamin Kreis, Brian Lee, Mia Liu, et al. 2019. FPGA-accelerated machine learning inference as a service for particle physics computing. Comput. Softw. Big Sci. 3, 1 (2019), 1–15.

[39]

Sankha Baran Dutta, Hoda Naghibijouybari, Nael Abu-Ghazaleh, Andres Marquez, and Kevin Barker. 2021. Leaky buddies: Cross-component covert channels on integrated CPU-GPU systems. In ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 972–984.

Digital Library

[40]

Ken Eguro and Ramarathnam Venkatesan. 2012. FPGAs for trusted cloud computing. In 22nd International Conference on Field Programmable Logic and Applications (FPL). 63–70.

[41]

Maik Ender, Amir Moradi, and Christof Paar. 2020. The unpatchable silicon: A full break of the bitstream encryption of Xilinx 7-series FPGAs. In 29th USENIX Security Symposium.

[42]

Haggai Eran, Lior Zeno, Maroun Tork, Gabi Malka, and Mark Silberstein. 2019. NICA: An infrastructure for inline acceleration of network applications. In USENIX Annual Technical Conference (USENIX ATC 19). 345–362.

Digital Library

[43]

Dieter Ernst. 2020. Competing in Artificial Intelligence Chips: China’s Challenge Amid Technology War. Centre for International Governance Innovation, Special Report.

[44]

Nariman Eskandari, Naif Tarafdar, Daniel Ly-Ma, and Paul Chow. 2019. A modular heterogeneous stack for deploying FPGAs and CPUs in the data center. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’19). ACM, New York, NY, 262–271. DOI:https://doi.org/10.1145/3289602.3293909

Digital Library

[45]

Suhaib A. Fahmy, Kizheppatt Vipin, and Shanker Shreejith. 2015. Virtualized FPGA accelerators for efficient cloud computing. In IEEE 7th International Conference on Cloud Computing Technology and Science (CloudCom). IEEE, 430–435.

Digital Library

[46]

Xin Fang, Stratis Ioannidis, and Miriam Leeser. 2017. Secure function evaluation using an FPGA overlay architecture. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 257–266.

Digital Library

[47]

Daniel Firestone, Andrew Putnam, Sambhrama Mundkur, Derek Chiou, Alireza Dabagh, Mike Andrewartha, Hari Angepat, Vivek Bhanu, Adrian Caulfield, Eric Chung et al. 2018. Azure accelerated networking: SmartNICs in the public cloud. In 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI 18). 51–66.

Digital Library

[48]

Forbes. 2018. Xilinx FPGAs: The Chip Behind Alibaba’s Singles Day. Retrieved from https://www.forbes.com/sites/moorinsights/2018/11/29/xilinx-fpgas-the-chip-behind-alibabas-singles-day/?sh=5f2294e27e3b.

[49]

Jeremy Fowers, Kalin Ovtcharov, Michael Papamichael, Todd Massengill, Ming Liu, Daniel Lo, Shlomi Alkalay, Michael Haselman, Logan Adams, Mahdi Ghandi, Stephen Heil, Prerak Patel, Adam Sapek, Gabriel Weisz, Lisa Woods, Sitaram Lanka, Steven K. Reinhardt, Adrian M. Caulfield, Eric S. Chung, and Doug Burger. 2018. A configurable cloud-scale DNN processor for real-time AI. In ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). 1–14. DOI:https://doi.org/10.1109/ISCA.2018.00012

Digital Library

[50]

Karl Freund. 2017. Google Cloud TPU: Strategic Implications for Google, NVIDIA and the Machine Learning Industry. Retrieved from https://www.forbes.com/sites/moorinsights/2017/05/22/google-cloud-tpu-strategic-implications-for-google-nvidia-and-the-machine-learning-industry/?sh=69d2f5a13af7.

[51]

Norihisa Fujita, Ryohei Kobayashi, Yoshiki Yamaguchi, and Taisuke Boku. 2019. Parallel processing on FPGA combining computation and communication in OpenCL programming. In IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE, 479–488.

[52]

Juan Fumero, Michail Papadimitriou, Foivos S. Zakkak, Maria Xekalaki, James Clarkson, and Christos Kotselidis. 2019. Dynamic application reconfiguration on heterogeneous hardware. In 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments. 165–178.

Digital Library

[53]

William Gayde. 2020. How Arm Came to Dominate the Mobile Market and It’s Coming for More, Much More. Retrieved from https://www.techspot.com/article/1989-arm-inside.

[54]

Alan George, Herman Lam, and Greg Stitt. 2010. Novo-G: At the forefront of scalable reconfigurable supercomputing. Comput. Sci. Eng. 13, 1 (2010), 82–86.

Digital Library

[55]

A. D. George, M. C. Herbordt, H. Lam, A. G. Lawande, J. Sheng, and C. Yang. 2016. Novo-G#: Large-scale reconfigurable computing with direct and programmable interconnects. In IEEE High Performance Extreme Computing Conference (HPEC). 1–7. DOI:https://doi.org/10.1109/HPEC.2016.7761639

[56]

Ehsan Ghasemi and Paul Chow. 2016. Accelerating Apache Spark big data analysis with FPGAs. In International IEEE Conferences on Ubiquitous Intelligence Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People, and Smart World Congress (UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld). 737–744. DOI:https://doi.org/10.1109/UIC-ATC-ScalCom-CBDCom-IoP-SmartWorld.2016.0119

[57]

Ehsan Ghasemi and Paul Chow. 2019. Accelerating Apache Spark with FPGAs. Concurr. Comput.: Pract. Exper. 31, 2 (2019), e4222. DOI:https://doi.org/10.1002/cpe.4222 arXiv:https://onlinelibrary.wiley.com/doi/pdf/10.1002/cpe.4222.

[58]

Ilias Giechaskiel, Kasper Rasmussen, and Jakub Szefer. 2019. Reading between the dies: Cross-SLR covert channels on multi-tenant cloud FPGAs. In IEEE International Conference on Computer Design. 1–10.

[59]

Ilias Giechaskiel, Kasper Rasmussen, and Jakub Szefer. 2020. CAPSULe: Cross-FPGA covert-channel attacks through power supply unit leakage. In IEEE Symposium on Security and Privacy. 1728–1741.

[60]

Ilias Giechaskiel, Kasper B. Rasmussen, and Ken Eguro. 2018. Leaky wires: Information leakage and covert communication between FPGA long wires. In Asia Conference on Computer and Communications Security (ASIACCS). 15–27.

Digital Library

[61]

AWS GitHub. 2020. AFI Power. Retrieved from https://github.com/aws/aws-fpga/blob/master/hdk/docs/afi_power.md.

[62]

Dennis R. E. Gnad, Fabian Oboril, and Mehdi B. Tahoori. 2017. Voltage drop-based fault attacks on FPGAs using valid bitstreams. In International Conference on Field Programmable Logic and Applications (FPL). 1–7.

[63]

Christoph Hagleitner, Dionysios Diamantopoulos, Burkhard Ringlein, Constantinos Evangelinos, Charles Johns, Rong N. Chang, Bruce D’Amora, James A. Kahle, James Sexton, Michael Johnston, Edward Pyzer-Knapp, and Chris Ward. 2021. Heterogeneous computing systems for complex scientific discovery workflows. In Design, Automation Test in Europe Conference Exhibition (DATE). 13–18. DOI:https://doi.org/10.23919/DATE51398.2021.9474061

[64]

S. Handagala, M. Herbordt, and M. Leeser. 2021. OCT: The open cloud FPGA testbed. In 31st International Conference on Field Programmable Logic and Applications (FPL).

[65]

Reiner Hartenstein. 2001. Coarse grain reconfigurable architecture (embedded tutorial). In Asia and South Pacific Design Automation Conference. ACM, 564–570.

Digital Library

[66]

Festus Hategekimana, Joel Mandebi Mbongue, Md Jubaer Hossain Pantho, and Christophe Bobda. 2018. Inheriting software security policies within hardware IP components. In IEEE International Symposium on Field-Programmable Custom Computing Machines. 53–56. DOI:https://doi.org/10.1109/FCCM.2018.00017

[67]

Festus Hategekimana, Joel Mandebi Mbongue, Md Jubaer Hossain Pantho, and Christophe Bobda. 2018. Secure hardware kernels execution in CPU+ FPGA heterogeneous cloud. In International Conference on Field-Programmable Technology (FPT). IEEE, 182–189.

[68]

Nicole Hemsothd. 2017. First in-depth look at Google’s new second-generation TPU. Retrieved from https://www.nextplatform.com/2017/05/17/first-depth-look-googles-new-second-generation-tpu/.

[69]

Edson L. Horta, John W. Lockwood, David E. Taylor, and David Parlour. 2002. Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. In 39th Annual Design Automation Conference (DAC’02). Association for Computing Machinery, New York, NY, 343–348. DOI:https://doi.org/10.1145/513918.514007

Digital Library

[70]

Kai Huang, Mehmet Gungor, Xin Fang, Stratis Ioannidis, and Miriam Leeser. 2019. Garbled circuits in the cloud using FPGA enabled nodes. In IEEE High Performance Extreme Computing Conference (HPEC). 1–6.

[71]

Ted Huffmire, Brett Brotherton, Nick Callegari, Jonathan Valamehr, Jeff White, Ryan Kastner, and Tim Sherwood. 2008. Designing secure systems on reconfigurable hardware. ACM Trans. Des. Autom. Electron. Syst. 13, 3 (July 2008), 44:1–44:24.

Digital Library

[72]

Siam U. Hussain, Bita Darvish Rouhani, Mohammad Ghasemzadeh, and Farinaz Koushanfar. 2018. Maxelerator: FPGA accelerator for privacy preserving multiply-accumulate (MAC) on cloud servers. In 55th Annual Design Automation Conference. 1–6.

Digital Library

[73]

Zsolt István, David Sidler, Gustavo Alonso, and Marko Vukolic. 2016. Consensus in a box: Inexpensive coordination in hardware. In 13th USENIX Symposium on Networked Systems Design and Implementation (NSDI’16). 425–438.

Digital Library

[74]

Chenglu Jin, Vasudev Gohil, Ramesh Karri, and Jeyavijayan Rajendran. 2020. Security of cloud FPGAs: A survey. arxiv arXiv:2005.04867 (2020).

[75]

Sang-Woo Jun, Shuotao Xu, and Arvind. 2017. Terabyte sort on FPGA-accelerated flash storage. In IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 17–24. DOI:https://doi.org/10.1109/FCCM.2017.53

[76]

Abdul Kabbani, Balajee Vamanan, Jahangir Hasan, and Fabien Duchene. 2014. FlowBender: Flow-level adaptive routing for improved latency and throughput in datacenter networks. In 10th ACM International Conference on Emerging Networking Experiments and Technologies (CoNEXT’14). Association for Computing Machinery, New York, NY, 149–160. DOI:https://doi.org/10.1145/2674005.2674985

Digital Library

[77]

Nachiket Kapre and Jan Gray. 2015. HopLite: Building austere overlay NOCs for FPGAs. In 25th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 1–8.

[78]

Ahmed Khawaja, Joshua Landgraf, Rohith Prakash, Michael Wei, Eric Schkufza, and Christopher J. Rossbach. 2018. Sharing, protection, and compatibility for reconfigurable fabric with Amorphos. In 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI’18). 107–127.

Digital Library

[79]

Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Jihye Lee, Donghyuk Lee, Chris B. Wilkerson, Konrad K. Lai, and Onur Mutlu. 2014. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. In International Symposium on Computer Architecture. 361–372.

Digital Library

[80]

Ryohei Kobayashi, Yuma Oobata, Norihisa Fujita, Yoshiki Yamaguchi, and Taisuke Boku. 2018. OpenCL-ready high speed FPGA network for reconfigurable high performance computing. In International Conference on High Performance Computing in Asia-Pacific Region. 192–201.

Digital Library

[81]

Paul Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom. 2019. Spectre attacks: Exploiting speculative execution. In 40th IEEE Symposium on Security and Privacy (S&P’19).

[82]

Dario Korolija, Timothy Roscoe, and Gustavo Alonso. 2020. Do OS abstractions make sense on FPGAs? In 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI’20). 991–1010.

Digital Library

[83]

S. Kumar Saha and C. Bobda. 2020. FPGA accelerated embedded system security through hardware isolation. In Asian Hardware Oriented Security and Trust Symposium (AsianHOST). 1–6. DOI:https://doi.org/10.1109/AsianHOST51057.2020.9358258

[84]

Joshua Landgraf, Tiffany Yang, Will Lin, Christopher J. Rossbach, and Eric Schkufza. 2021. Compiler-driven FPGA virtualization with SYNERGY. In 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems. 818–831.

Digital Library

[85]

Xiangwei Li, Abhishek Jain, Douglas Maskell, and Suhaib A. Fahmy. 2016. An area-efficient FPGA overlay using DSP block based time-multiplexed functional units. arXiv preprint arXiv:1606.06460 (2016).

[86]

Thomas Lin, Byungchul Park, Hadi Bannazadeh, and Alberto Leon-Garcia. 2015. Savi testbed architecture and federation. In Future Access Enablers of Ubiquitous and Intelligent Infrastructures. Springer, 3–10.

[87]

Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Anders Fogh, Jann Horn, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. 2018. Meltdown: Reading kernel memory from user space. In 27th USENIX Security Symposium (USENIX Security’18).

Digital Library

[88]

Peter Loscocco and Stephen Smalley. 2001. Meeting critical security objectives with security-enhanced Linux. In Ottawa Linux Symposium. 115–134.

[89]

Layong Larry Luo and T. E. G. Tencent. 2018. In Towards Converged SmartNIC Architecture for Bare Metal and Public Clouds at Tencent Scale 2nd Asia-Pacific Workshop on Networking (APNet 2018) August 2-3 2018, Beijing, China.

[90]

Jiacheng Ma, Gefei Zuo, Kevin Loughlin, Xiaohe Cheng, Yanqiang Liu, Abel Mulugeta Eneyew, Zhengwei Qi, and Baris Kasikci. 2020. A hypervisor for shared-memory FPGA platforms. In 25th International Conference on Architectural Support for Programming Languages and Operating Systems. 827–844.

Digital Library

[91]

M. Ma and V. W. S. Wong. 2019. An optimal peak hour content server cache update scheduling algorithm for 5G hetnets. In IEEE International Conference on Communications (ICC). 1–6. DOI:https://doi.org/10.1109/ICC.2019.8761705

[92]

Sen Ma, Zeyad Aklah, and David Andrews. 2015. A run time interpretation approach for creating custom accelerators. In 25th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 1–4.

Digital Library

[93]

Divya Mahajan, Joon Kyung Kim, Jacob Sacks, Adel Ardalan, Arun Kumar, and Hadi Esmaeilzadeh. 2018. In-RDBMS hardware acceleration of advanced analytics. Proc. VLDB Endow. 11, 11 (July 2018), 1317–1331.

Digital Library

[94]

Mallik Mahalingam, Dinesh G. Dutt, Kenneth Duda, Puneet Agarwal, Lawrence Kreeger, T. Sridhar, Mike Bursell, and Chris Wright. 2014. Virtual eXtensible local area network (VXLAN): A framework for overlaying virtualized layer 2 networks over layer 3 networks. RFC 7348 (2014), 1–22.

[95]

Pongstorn Maidee, Alireza Kaviani, and Kevin Zeng. 2017. LinkBlaze: Efficient global data movement for FPGAs. In International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 1–8.

[96]

Joel Mandebi Mbongue, Sujan Kumar Saha, and Christophe Bobda. 2021. Domain isolation in FPGA-accelerated cloud and data center applications. In Great Lakes Symposium on VLSI. 283–288.

Digital Library

[97]

Joel Mandebi Mbongue, Danielle Tchuinkou Kwadjo, and Christophe Bobda. 2018. FLexiTASK: A flexible FPGA overlay for efficient multitasking. In Great Lakes Symposium on VLSI. ACM, 483–486.

Digital Library

[98]

Joel Mbongue, Festus Hategekimana, Danielle Tchuinkou Kwadjo, David Andrews, and Christophe Bobda. 2018. FPGAVirt: A novel virtualization framework for FPGAs in the cloud. In IEEE 11th International Conference on Cloud Computing (CLOUD). IEEE, 862–865.

[99]

Joel Mandebi Mbongue, Danielle Tchuinkou Kwadjo, and Christophe Bobda. 2019. Automatic generation of application-specific FPGA overlays with Rapidwright. In International Conference on Field-Programmable Technology (ICFPT). IEEE, 303–306.

Digital Library

[100]

Joel Mandebi Mbongue, Danielle Tchuinkou Kwadjo, Alex Shuping, and Christophe Bobda. 2021. Deploying multi-tenant FPGAs within Linux-based cloud infrastructure. ACM Trans. Reconfig. Technol. Syst. 15, 2 (2021), 1–31.

Digital Library

[101]

Joel Mandebi Mbongue, Sujan Kumar Saha, and Christophe Bobda. 2021. Performance study of multi-tenant cloud FPGAs. In IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE, 168–171.

[102]

Joel Mandebi Mbongue, Sujan Kumar Saha, and Christophe Bobda. 2021. A security architecture for domain isolation in multi-tenant cloud FPGAs. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 290–295.

[103]

Joel Mandebi Mbongue, Alex Shuping, Pankaj Bhowmik, and Christophe Bobda. 2020. Architecture support for FPGA multi-tenancy in the cloud. In IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 125–132.

[104]

Thierry Moreau, Tianqi Chen, Luis Vega, Jared Roesch, Eddie Yan, Lianmin Zheng, Josh Fromm, Ziheng Jiang, Luis Ceze, Carlos Guestrin, and Arvind Krishnamurthy. 2019. A hardware-software blueprint for flexible deep learning specialization. IEEE Micro 39, 5 (2019), 8–16. DOI:https://doi.org/10.1109/MM.2019.2928962

[105]

Jad Naous, David Erickson, G. Adam Covington, Guido Appenzeller, and Nick McKeown. 2008. Implementing an OpenFlow switch on the NetFPGA platform. In 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems. 1–9.

Digital Library

[106]

Gil Neiger, Amy Santoni, Felix Leung, Dion Rodgers, and Rich Uhlig. 2006. Intel virtualization technology: Hardware support for efficient processor virtualization. Intel Technol. J. 10, 3 (2006).

[107]

Jonas Ney, Dominik Loroch, Vladimir Rybalkin, Nico Weber, Jens Krüger, and Norbert Wehn. 2021. HALF: Holistic auto machine learning for FPGAs. In st IEEE International Conference on Field-Programmable Logic and Applications (FPL). DOI:https://doi.org/10.1109/FPL53798.2021.00069

[108]

M. Noormohammadpour and C. S. Raghavendra. 2018. Datacenter traffic control: Understanding techniques and tradeoffs. IEEE Commun. Surv. Tutor. 20, 2 (2018), 1492–1525. DOI:https://doi.org/10.1109/COMST.2017.2782753

[109]

Opeyemi Osanaiye, Kim-Kwang Raymond Choo, and Mqhele Dlodlo. 2016. Distributed denial of service (DDoS) resilience in cloud: Review and conceptual cloud DDoS mitigation framework. J. Netw. Comput. Applic. 67 (May 2016), 147–165.

Digital Library

[110]

Phitchaya Mangpo Phothilimthana, Ming Liu, Antoine Kaufmann, Simon Peter, Rastislav Bodik, and Thomas Anderson. 2018. FLOEM: A programming system for NIC-accelerated network applications. In 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI’18). 663–679.

Digital Library

[111]

Christian Pilato, Stanislav Bohm, Fabien Brocheton, Jeronimo Castrillon, Riccardo Cevasco, Vojtech Cima, Radim Cmar, Dionysios Diamantopoulos, Fabrizio Ferrandi, Jan Martinovic, Gianluca Palermo, Michele Paolino, Antonio Parodi, Lorenzo Pittaluga, Daniel Raho, Francesco Regazzoni, Katerina Slaninova, and Christoph Hagleitner. 2021. EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms. In Design, Automation Test in Europe Conference Exhibition (DATE). 1320–1325. DOI:https://doi.org/10.23919/DATE51398.2021.9473940

[112]

Christian Plessl. 2018. Bringing FPGAs to HPC production systems and codes. In H2RC’18 Workshop at Supercomputing (SC’18). DOI:https://doi.org/10.13140/RG.2.2.34327.42407

[113]

George Provelengios, Daniel Holcomb, and Russell Tessier. 2019. Characterizing power distribution attacks in multi-user FPGA environments. In International Conference on Field Programmable Logic and Applications (FPL). 194–201.

[114]

George Provelengios, Daniel Holcomb, and Russell Tessier. 2020. Power wasting circuits for cloud FPGA attacks. In International Conference on Field Programmable Logic and Applications (FPL).

[115]

A. Putnam, A. M. Caulfield, E. S. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G. P. Gopal, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. Smith, J. Thong, P. Y. Xiao, and D. Burger. 2014. A reconfigurable fabric for accelerating large-scale data center services. In ACM/IEEE 41st International Symposium on Computer Architecture (ISCA). 13–24. DOI:https://doi.org/10.1109/ISCA.2014.6853195

Digital Library

[116]

Arzhang Rafii, Welson Sun, and Paul Chow. 2021. Pharos: A multi-FPGA performance monitor. In 31st International Conference on Field-Programmable Logic and Applications (FPL). 257–262. DOI:https://doi.org/10.1109/FPL53798.2021.00048

[117]

Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sébastien Pillement, Daniel Holcomb, and Russell Tessier. 2018. FPGA side channel attacks without physical access. In IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 45–52.

[118]

Kasper Rasmussen, Ilias Giechaskiel, and Ken Eguro. 2019. Leakier wires: Exploiting FPGA long wires for covert-and side-channel attacks. ACM Trans. Reconfig. Technol. Syst. 12, 3 (2019), 11:1–11.29.

Digital Library

[119]

Sandip Ray and Yier Jin. 2015. Security policy enforcement in modern SoC designs. In IEEE/ACM International Conference on Computer-Aided Design. 345–350.

Digital Library

[120]

M. Sadegh Riazi, Kim Laine, Blake Pelton, and Wei Dai. 2020. Heax: An architecture for computing on encrypted data. In 25th International Conference on Architectural Support for Programming Languages and Operating Systems. 1295–1309.

Digital Library

[121]

B. Ringlein, F. Abel, D. Diamantopoulos, B. Weiss, C. Hagleitner, M. Reichenbach, and D. Fey. 2021. A case for function-as-a-service with Disaggregated FPGAs. In IEEE 14th International Conference on Cloud Computing (CLOUD’21). 333–344. DOI:https://doi.org/10.1109/CLOUD53861.2021.00047

[122]

Burkhard Ringlein, Francois Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, and Dietmar Fey. 2019. System architecture for network-attached FPGAs in the cloud using partial reconfiguration. In 29th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 293–300. DOI:https://doi.org/10.1109/FPL.2019.00054

[123]

B. Ringlein, F. Abel, A. Ditter, B. Weiss, C. Hagleitner, and D. Fey. 2020. Programming reconfigurable heterogeneous computing clusters using MPI with transpilation. In IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC). IEEE, 1–9. DOI:https://doi.org/10.1109/H2RC51942.2020.00006

[124]

B. Ringlein, F. Abel, A. Ditter, B. Weiss, C. Hagleitner, and D. Fey. 2020. ZRLMPI: A unified programming model for reconfigurable heterogeneous computing clusters. In IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 220. DOI:https://doi.org/10.1109/FCCM48280.2020.00051

[125]

John M. Rushby. 1982. Proof of separability a verification technique for a class of security kernels. In International Symposium on Programming. 352–367.

Digital Library

[126]

Sahand Salamat, Armin Haj Aboutalebi, Behnam Khaleghi, Joo Hwan Lee, Yang Seok Ki, and Tajana Rosing. 2021. NASCENT: Near-storage acceleration of database sort on SmartSSD. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’21). 262–272.

Digital Library

[127]

Grigory Sapunov. 2021. Will ASIC Chips Become the Next Big Thing in AI? Retrieved from https://moorinsightsstrategy.com/will-asic-chips-become-the-next-big-thing-in-ai/.

[128]

Falk Schellenberg, Dennis R. E. Gnad, Amir Moradi, and Mehdi B. Tahoori. 2018. An inside job: Remote power analysis attacks on FPGAs. In Design, Automation & Test in Europe Conference & Exhibition (DATE). 1111–1116.

[129]

Omar Sefraoui, Mohammed Aissaoui, and Mohsine Eleuldj. 2012. OpenStack: Toward an open-source solution for cloud computing. Int. J. Comput. Applic. 55, 3 (2012), 38–42.

[130]

Hardik Sharma, Jongse Park, Divya Mahajan, Emmanuel Amaro, Joon Kyung Kim, Chenkai Shao, Asit Mishra, and Hadi Esmaeilzadeh. 2016. From high-level deep neural models to FPGAs. In 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 1–12.

Digital Library

[131]

S. B. Shaw, C. Kumar, and A. K. Singh. 2017. Use of time-series based forecasting technique for balancing load and reducing consumption of energy in a cloud data center. In International Conference on Intelligent Computing and Control (I2C2). 1–6. DOI:https://doi.org/10.1109/I2C2.2017.8321782

[132]

Jim Smith and Ravi Nair. 2005. Virtual Machines: Versatile Platforms for Systems and Processes. Elsevier.

Digital Library

[133]

Hayden Kwok-Hay So and Cheng Liu. 2016. FPGA overlays. In FPGAs for Software Programmers. Springer, 285–305.

Digital Library

[134]

Mengshu Sun, Pu Zhao, Mehmet Gungor, Massoud Pedram, Miriam Leeser, and Xue Lin. 2020. 3D CNN acceleration on FPGA using hardware-aware pruning. In 57th ACM/IEEE Design Automation Conference (DAC). 1–6.

Digital Library

[135]

Jakub Szefer. 2019. Survey of microarchitectural side and covert channels, attacks, and defenses. J. Hardw. Syst. Secur. 3, 3 (Sept. 2019), 219–234.

[136]

David Talbot. 2009. Vulnerability Seen in Amazon’s Cloud-Computing. Retrieved from https://www. technologyreview.com/2009/10/23/208662/vulnerability-seen-in-amazons-cloud-computing/.

[137]

Naif Tarafdar and Paul Chow. 2019. libGalapagos: A software environment for prototyping and creating heterogeneous FPGA and CPU applications. In 6th International Workshop on FPGAs for Software Programmers (FSP’19).

[138]

Naif Tarafdar, Nariman Eskandari, Thomas Lin, and Paul Chow. 2017. Designing for FPGAs in the cloud. IEEE Des. Test 35, 1 (2017), 23–29.

[139]

N. Tarafdar, N. Eskandari, V. Sharma, C. Lo, and P. Chow. 2018. Galapagos: A full stack approach to FPGA integration in the cloud. IEEE Micro 38, 06 (Nov. 2018), 18–24. DOI:https://doi.org/10.1109/MM.2018.2877290

[140]

Naif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, and Paul Chow. 2017. Enabling flexible network FPGA clusters in a heterogeneous cloud data center. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 237–246.

Digital Library

[141]

Naif Tarafdar, Thomas Lin, Daniel Ly-Ma, Daniel Rozhko, Alberto Leon-Garcia, and Paul Chow. 2019. Building the infrastructure for deploying FPGAs in the cloud. In Hardware Accelerators in Data Centers. Springer, 9–33.

[142]

Impulse Accelerated Technologies. 2021. Retrieved from https://web.archive.org/web/20110904033728http://www.impulseaccelerated.com/.

[143]

The Apache Software Foundation / TVM community. [n.d.]. Quick Start Tutorial for Compiling Deep Learning Models. Retrieved from https://tvm.apache.org/docs/tutorial/relay_quick_start.html.

[144]

Shanquan Tian, Ilias Giechaskiel, Wenjie Xiong, and Jakub Szefer. 2021. Cloud FPGA cartography using PCIe contention. In IEEE International Symposium on Field-Programmable Custom Computing Machines.

[145]

Shanquan Tian and Jakub Szefer. 2019. Temporal thermal covert channels in cloud FPGAs. In International Symposium on Field-Programmable Gate Arrays (FPGA).

Digital Library

[146]

Shanquan Tian, Wenjie Xiong, Ilias Giechaskiel, Kasper Rasmussen, and Jakub Szefer. 2020. Fingerprinting cloud FPGA infrastructures. In International Symposium on Field-Programmable Gate Arrays (FPGA).

Digital Library

[147]

Furkan Turan, Sujoy Sinha Roy, and Ingrid Verbauwhede. 2020. HEAWS: An accelerator for homomorphic encryption on the Amazon AWS FPGA. IEEE Trans. Comput. 69, 8 (2020), 1185–1196.

[148]

Furkan Turan and Ingrid Verbauwhede. 2020. Trust in FPGA-accelerated cloud computing. Comput. Surv. 53, 6 (Dec. 2020), 28:1–28:128.

Digital Library

[149]

Mohammad Usmani, Shahrzad Keshavarz, Eric Matthews, Lesley Shannon, Russell Tessier, and Daniel E. Holcomb. 2019. Efficient PUF-based key generation in FPGAs using per-device configuration. IEEE Trans. VLSI Syst. 27, 2 (Feb. 2019), 364–375.

[150]

Juan Camilo Vega, Qianfeng Clark Shen, Alberto Leon-Garcia, and Paul Chow. 2019. Introducing ReCPRI: A field re-configurable protocol for backhaul communication in a radio access network. In IFIP/IEEE Symposium on Integrated Network and Service Management (IM). 329–336.

[151]

Malte Vesper, Dirk Kocha, and Khoa Phama. 2017. PCIeHLS: An OpenCL HLS framework. In 4th International Workshop on FPGAs for Software Programmers. VDE, 1–6.

[152]

Hasitha Muthumala Waidyasooriya and Masanori Hariyama. 2019. Multi-FPGA accelerator architecture for stencil computation exploiting spacial and temporal scalability. IEEE Access 7 (2019), 53188–53201.

[153]

Herbert Walder and Marco Platzner. 2004. A runtime environment for reconfigurable hardware operating systems. In Field Programmable Logic and Application, Jürgen Becker, Marco Platzner, and Serge Vernalde (Eds.). Springer Berlin, 831–835.

[154]

Tianqi Wang, Tong Geng, Ang Li, Xi Jin, and Martin Herbordt. 2020. FPDeep: Scalable acceleration of CNN training on deeply-pipelined FPGA clusters. IEEE Trans. Comput. 69, 8 (2020), 1143–1158.

Digital Library

[155]

X. Wang, Y. Niu, F. Liu, and Z. Xu. 2020. When FPGA meets cloud: A first look at performance. IEEE Trans. Cloud Comput. (2020), 1–1. DOI:https://doi.org/10.1109/TCC.2020.2992548

[156]

Greg Watson, Nick McKeown, and Martin Casado. 2006. NetFPGA: A tool for network research and education. In 2nd Workshop on Architectural Research Using FPGA Platforms (WARFP), Vol. 3.

[157]

J. Weerasinghe, F. Abel, C. Hagleitner, and A. Herkersdorf. 2015. Enabling FPGAs in hyperscale data centers. In IEEE 12th International Conference on Ubiquitous Intelligence and Computing and IEEE 12th International Conference on Autonomic and Trusted Computing and IEEE 15th International Conference on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom). 1078–1086. DOI:https://doi.org/10.1109/UIC-ATC-ScalCom-CBDCom-IoP.2015.199

[158]

J. Weerasinghe, F. Abel, C. Hagleitner, and A. Herkersdorf. 2016. Disaggregated FPGAs: Network performance comparison against bare-metal servers, virtual machines and Linux containers. In IEEE International Conference on Cloud Computing Technology and Science (CloudCom). 9–17. DOI:https://doi.org/10.1109/CloudCom.2016.0018

[159]

J. Weerasinghe, R. Polig, F. Abel, and C. Hagleitner. 2016. Network-attached FPGAs for data center applications. In International Conference on Field-Programmable Technology (FPT). 36–43. DOI:https://doi.org/10.1109/FPT.2016.7929186

[160]

David Wilson and Greg Stitt. 2019. Seiba: An FPGA overlay-based approach to rapid application development. In International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 1–8.

[161]

Xilinx Case Study. [n.d.]. Xilinx Powers Alibaba Cloud FaaS with AI Acceleration Solution for E-Commerce Business. Retrieved from https://www.xilinx.com/publications/powered-by-xilinx/xilinx-alibaba-case-study.pdf.

[162]

Xilinx Corporation 2021. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics.

[163]

Wang Xu. 2018. Hardware acceleration over NFV in China Mobile. OPNFV Plugfest.

[164]

Xiaoyu Yu, Yuwei Wang, Jie Miao, Ephrem Wu, Heng Zhang, Yu Meng, Bo Zhang, Biao Min, Dewei Chen, and Jianlin Gao. 2019. A data-center FPGA acceleration platform for convolutional neural networks. In 29th International Conference on Field Programmable Logic and Applications (FPL). 151–158.

[165]

Shaza Zeitouni, Ghada Dessouky, and Ahmad-Reza Sadeghi. 2020. SoK: On the security challenges and risks of multi-tenant FPGAs in the cloud. arxiv arXiv:2009.13914 (2020).

[166]

Shaza Zeitouni, Jo Vliegen, Tommaso Frassetto, Dirk Koch, Ahmad-Reza Sadeghi, and Nele Mentens. 2021. Trusted configuration in cloud FPGAs. In IEEE International Symposium on Field-Programmable Custom Computing Machines.

[167]

Jiansong Zhang, Yongqiang Xiong, Ningyi Xu, Ran Shu, Bojie Li, Peng Cheng, Guo Chen, and Thomas Moscibroda. 2017. The Feniks FPGA operating system for cloud computing. In 8th Asia-Pacific Workshop on Systems. 1–7.

Digital Library

[168]

Ke Zhang, Yisong Chang, Mingyu Chen, Yungang Bao, and Zhiwei Xu. 2019. Computer organization and design course with FPGA cloud. In 50th ACM Technical Symposium on Computer Science Education. ACM, 927–933.

Digital Library

[169]

Mark Zhao and G. Edward Suh. 2018. FPGA-based remote power side-channel attacks. In IEEE Symposium on Security and Privacy (S&P). 229–244.

[170]

Noa Zilberman, Yury Audzevich, G. Adam Covington, and Andrew W. Moore. 2014. NetFPGA SUME: Toward 100 Gbps as research commodity. IEEE Micro 34, 5 (2014), 32–41.

[171]

Xiantao Zxt, Zhengxiao Zx, and Justin Song. 2020. High-density multi-tenant bare-metal cloud with memory expansion SoC and power management. In IEEE Hot Chips 32 Symposium (HCS). 1–18. DOI:https://doi.org/10.1109/HCS49909.2020.9220447

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cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 15, Issue 3

September 2022

353 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/3508070

Editor:
Deming Chen
University of Illinois, Urbana-Champaign Urbana, USA

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Publication History

Published: 04 February 2022

Accepted: 01 December 2021

Revised: 01 October 2021

Received: 01 July 2021

Published in TRETS Volume 15, Issue 3

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