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Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net

Published: 22 December 2022 Publication History

Abstract

An accurate DRC (design rule check) hotspot prediction at the placement stage is essential in order to reduce a substantial amount of design time required for the iterations of placement and routing. It is known that for implementing chips with advanced technology nodes, (1) pin accessibility and (2) routing congestion are two major causes of DRVs (design rule violations). Though many ML (machine learning) techniques have been proposed to address this prediction problem, it was not easy to assemble the aggregate data on items 1 and 2 in a unified fashion for training ML models, resulting in a considerable accuracy loss in DRC hotspot prediction. This work overcomes this limitation by proposing a novel ML based DRC hotspot prediction technique, which is able to accurately capture the combined impact of items 1 and 2 on DRC hotspots. Precisely, we devise a graph, called pin proximity graph, that effectively models the spatial information on cell I/O pins and the information on pin-to-pin disturbance relation. Then, we propose a new ML model, called PGNN, which tightly combines GNN (graph neural network) and U-net in a way that GNN is used to embed pin accessibility information abstracted from our pin proximity graph while U-net is used to extract routing congestion information from grid-based features. Through experiments with a set of benchmark designs using Nangate 15nm library, our PGNN outperforms the existing ML models on all benchmark designs, achieving on average 7.8~12.5% improvements on F1-score while taking 5.5× fast inference time in comparison with that of the state-of-the-art techniques.

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  • (2024)Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability OptimizationProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3633312(205-212)Online publication date: 12-Mar-2024
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  • (2024)Preventing short violations in clock routing with an SVM classifier before powerplanning and placementMicroelectronics Journal10.1016/j.mejo.2024.106429153(106429)Online publication date: Nov-2024
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cover image ACM Conferences
ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design
October 2022
1467 pages
ISBN:9781450392174
DOI:10.1145/3508352
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • IEEE-EDS: Electronic Devices Society
  • IEEE CAS
  • IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 December 2022

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ICCAD '22
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ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design
October 30 - November 3, 2022
California, San Diego

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

View all
  • (2024)Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability OptimizationProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3633312(205-212)Online publication date: 12-Mar-2024
  • (2024)Pre-route timing prediction and optimization with graph neural network modelsIntegration, the VLSI Journal10.1016/j.vlsi.2024.10226299:COnline publication date: 1-Nov-2024
  • (2024)Preventing short violations in clock routing with an SVM classifier before powerplanning and placementMicroelectronics Journal10.1016/j.mejo.2024.106429153(106429)Online publication date: Nov-2024
  • (2023)Machine Learning in EDA: When and How2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD58807.2023.10299822(1-6)Online publication date: 10-Sep-2023
  • (2023)AI-EDA: Toward a Holistic Approach to AI-Powered EDA2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD58807.2023.10299815(1-3)Online publication date: 10-Sep-2023
  • (2023)ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323942(1-9)Online publication date: 28-Oct-2023
  • (2023)Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323800(1-9)Online publication date: 28-Oct-2023
  • (2023)Routability Prediction and Optimization Using Explainable AI2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323630(1-8)Online publication date: 28-Oct-2023

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