Jai-Ming Lin
ABSTRACT
Although the 3D integrated circuit (IC) placement problem has been studied for many years, few publications devoted to the macro legalization. Due to large sizes of macros, the macro placement problem is harder than cell placement, especially when preplaced macros exist in a multi-tier structure. In order to have a more global view, this paper proposes the partitioning-last macro-first flow to handle 3D placement for mixed-size designs, which performs tier partitioning after placement prototyping and then legalizes macros before cell placement. A novel two-step approach is proposed to handle 3D macro placement. The first step determines locations of macros in a projection plane based on a new representation, named K-tier Partially Occupied Corner Stitching. It not only can keep the prototyping result but also guarantees a legal placement after tier assignment of macros. Next, macros are assigned to respective tiers by Integer Linear Programming (ILP) algorithm. Experimental results show that our design flow can obtain better solutions than other flows especially in the cases with more preplaced macros.
- Synopsys Inc. https://www.synopsys.com/company.html.Google Scholar
- IBM Inc. https://www.ibm.com/analytics/cplex-optimizer.Google Scholar
- Himax Technologies, Inc. https://www.himax.com.tw/zh/company/about-himax/.Google Scholar
- L. Bamberg, A. Garcia-Ortiz, L. Zhu, S. Pentapati, D. E. Shim, and S. K. Lim, "Macro-3D: A Physical Design Methodology for Face-to-face-stacked Heterogeneous 3D ICs," in Proc. of DATE, pp. 37--42, Mar. 2020.Google Scholar
- C.-H. Chang, Y.-W. Chang, and T.-C. Cheng, "A Novel Damped-wave Framework for Macro Placement," in Proc. of ICCAD, pp. 504--511, 2017.Google Scholar
- K. Chang, S. Sinha, B. Cline, R. Southerland, M. Doherty, G. Yeric, and S. K. Lim, "Cascade2D: A Design-aware Partitioning Approach to Monolithic 3D IC with 2D Commercial Tools," in Proc. of ICCAD, pp. 1--8, 2016.Google Scholar
- Y.-F. Chen, C.-C. Huang, C.-H. Chiou, Y.-W. Chang, and C.-J. Wang, "Routability-driven Blockage-aware Macro Placement," in Proc. of DAC, pp. 1--6, 2014.Google Scholar
- T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang, and T.-Y. Liu, "MP-trees: A Packing-based Macro Placement Algorithm for Modern Mixed-size Designs," IEEE TCAD, vol. 27, no. 9, pp. 1621--1634, 2008.Google ScholarDigital Library
- C.-H Chiou, C.-H Chang, S.-T Chen, and Y.-W Chang, "Circular-contour-based Obstacle-aware Macro Placement," in Proc. of ASP-DAC, pp. 172--177, 2016.Google Scholar
- J. Cong and G. Luo, "An Analytical Placer for Mixed-size 3D Placement," in Proc. of ISPD, pp. 61--66, 2010.Google Scholar
- G. Karypis and V. Kumar, "hMETIS, a hypergraph partitioning package version 1.5.3," http://glaros.dtc.umn.edu/gkhome/metis/hmetis/download.Google Scholar
- B. W. Ku, K. Chang, and S. K. Lim, "Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-face-bonded 3D ICs," in Proc. of ISPD, pp. 90--97, 2018.Google Scholar
- J.-M. Lin, S.-T. Li, and Y.-T. Wang, "Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity between Macros," in Proc. of DAC, pp. 1--6, Jun. 2019.Google Scholar
- J.-M. Lin, Y.-L. Deng, Y.-C. Yang, J.-J. Chen and Y.-C. Chen, "A Novel Macro Placement Approach based on Simulated Evolution Algorithm," in Proc. of ICCAD, pp. 1--7, Nov. 2019.Google Scholar
- J.-M. Lin, Y.-L. Deng, Y.-C. Yang, and J.-J. Chen, P.-C. Lu, "Dataflow-aware Macro Placement based on Simulated Evolution Algorithm for Mixed-Size Designs," IEEE TVLS, vol. 29, No. 5, pp. 973--984, May. 2021.Google Scholar
- J. Lu, H. Zhuang, I. Kang, P. Chen, and C.-K. Cheng, "ePlace-3D: Electrostatics Based Placement for 3D-ICs," in Proc. of ISPD, pp. 11--18, 2016.Google Scholar
- G. Luo, Y. Shi, and J. Cong, "An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness," IEEE TCAD, vol. 32, no. 4, pp. 510--523, 2013.Google Scholar
- J. K. Ousterhout, "Corner Stitching: A Data-structuring Technique for VLSI Layout Tools," IEEE TCAD, vol. 3, no. 1, pp. 87--100, 1984.Google ScholarDigital Library
- S. Panth, K. Samadi, Y. Du and S. K. Lim, "Shrunk-2D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3D ICs," IEEE TCAD, vol. 36, no. 10, pp. 1716--1724, 2017.Google Scholar
Index Terms
- A Novel Blockage-Avoiding Macro Placement Approach for 3D ICs Based on POCS
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