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How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning

Authors:

Prianka Sengupta,

Jiang HuAuthors Info & Claims

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

Article No.: 89, Pages 1 - 9

https://doi.org/10.1145/3508352.3549375

Published: 22 December 2022 Publication History

Abstract

Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to considerably different design quality and performance-power tradeoff. In general, the impact of HDL coding is not clear until logic synthesis or even layout is completed. However, running synthesis merely as a feedback for HDL code is computationally not economical especially in early design phases when the code needs to be frequently modified. Furthermore, in late stages of design convergence burdened with high-impact engineering change orders (ECO's), design iterations become prohibitively expensive. To this end, we propose a machine learning approach to Verilog-based Register-Transfer Level (RTL) design assessment without going through the synthesis process. It would allow designers to quickly evaluate the performance-power tradeoff among different options of RTL designs. Experimental results show that our proposed technique achieves an average of 95% prediction accuracy in terms of post-placement analysis, and is 6 orders of magnitude faster than evaluation by running logic synthesis and placement.

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Cited By

Lu YZhang QXie ZDev KYoo JMeinerzhagen P(2024)Unleashing Flexibility of ML-based Power Estimators Through Efficient Development StrategiesProceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design10.1145/3665314.3670823(1-6)Online publication date: 9-Sep-2024
https://doi.org/10.1145/3665314.3670823
Esmaeilzadeh HGhodrati SKahng AKim JKinzer SKundu SMahapatra RManasi SSapatnekar SWang ZZeng Z(2024)An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning AcceleratorsACM Transactions on Design Automation of Electronic Systems10.1145/366465229:4(1-33)Online publication date: 9-Jul-2024
https://dl.acm.org/doi/10.1145/3664652
Chen CHu GZuo DYu CMa YZhang HDe V(2024)E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic SynthesisProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3656246(1-6)Online publication date: 7-Nov-2024
https://doi.org/10.1145/3649329.3656246
Show More Cited By

Index Terms

How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation

Index terms have been assigned to the content through auto-classification.

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Published In

cover image ACM Conferences

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

October 2022

1467 pages

ISBN:9781450392174

DOI:10.1145/3508352

Conference Chair:
Tulika Mitra
National University of Singapore
,
Program Chairs:
Evangeline Young
The Chinese University of Hong Kong
,
Jinjun Xiong
University at Buffalo (UB)

Copyright © 2022 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE-EDS: Electronic Devices Society
IEEE CAS
IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 December 2022

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ICCAD '22

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SIGDA

ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design

October 30 - November 3, 2022

California, San Diego

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Lu YZhang QXie ZDev KYoo JMeinerzhagen P(2024)Unleashing Flexibility of ML-based Power Estimators Through Efficient Development StrategiesProceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design10.1145/3665314.3670823(1-6)Online publication date: 9-Sep-2024
https://doi.org/10.1145/3665314.3670823
Esmaeilzadeh HGhodrati SKahng AKim JKinzer SKundu SMahapatra RManasi SSapatnekar SWang ZZeng Z(2024)An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning AcceleratorsACM Transactions on Design Automation of Electronic Systems10.1145/366465229:4(1-33)Online publication date: 9-Jul-2024
https://dl.acm.org/doi/10.1145/3664652
Chen CHu GZuo DYu CMa YZhang HDe V(2024)E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic SynthesisProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3656246(1-6)Online publication date: 7-Nov-2024
https://doi.org/10.1145/3649329.3656246
Fang WLiu SZhang HXie ZDe V(2024)Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early OptimizationProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655671(1-6)Online publication date: 7-Nov-2024
https://doi.org/10.1145/3649329.3655671
Lopera DEcker W(2024)AI-Enabled Static Timing Analysis at Early Stages of the Digital Design FlowAI-Enabled Electronic Circuit and System Design10.1007/978-3-031-71436-8_4(109-154)Online publication date: 17-Oct-2024
https://doi.org/10.1007/978-3-031-71436-8_4
Alcorta Lozano EGerstlauer ADeng CSun QZhang ZXu CWills LSanchez Lopera DEcker WGarg SHu JAl Faruque MHu X(2023)Special Session: Machine Learning for Embedded System DesignProceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis10.1145/3607888.3608962(28-37)Online publication date: 17-Sep-2023
https://dl.acm.org/doi/10.1145/3607888.3608962
Xie ZChinnery DHui-Ru Jiang I(2023)Efficient Runtime Power Modeling with On-Chip Power MetersProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3578927(168-174)Online publication date: 26-Mar-2023
https://dl.acm.org/doi/10.1145/3569052.3578927
Ouyang YLi SZuo DFan HMa Y(2023)ASAP: Accurate Synthesis Analysis and Prediction with Multi-Task Learning2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD58807.2023.10299840(1-6)Online publication date: 10-Sep-2023
https://doi.org/10.1109/MLCAD58807.2023.10299840
Hu JKahng A(2023)Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323684(1-7)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323684

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