skip to main content
10.1145/3508352.3549383acmconferencesArticle/Chapter ViewAbstractPublication PagesiccadConference Proceedingsconference-collections
research-article

X-Check: GPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms

Published: 22 December 2022 Publication History

Abstract

Design rule checking (DRC) is essential in physical verification to ensure high yield and reliability for VLSI circuit designs. To achieve reasonable design cycle time, acceleration for computationally intensive DRC tasks has been demanded to accommodate the ever-growing complexity of modern VLSI circuits. In this paper, we propose X-Check, a GPU-accelerated design rule checker. X-Check integrates novel parallel sweepline algorithms, which are both efficient in practice and with nontrivial theoretical guarantees. Experimental results have demonstrated significant speedup achieved by X-Check compared with a multi-threaded CPU checker.

References

[1]
J. L. Bentley and D. Wood, "An optimal worst case algorithm for reporting intersections of rectangles," IEEE Transactions on Computers, vol. 29, no. 07, pp. 571--577, 1980.
[2]
U. Lauther, "An o (n log n) algorithm for boolean mask operations," in Proc. DAC, 1981, p. 555--562.
[3]
M. Sato, J. Kim, T. Awashima, and T. Ohtsuki, "A theoretically optimal and practically fast algorithm for vlsi geometrical design rule verification," in Proc. ISCAS, 1988, pp. 1445--1448.
[4]
C. R. Bonapace and C.-Y. Lo, "An o (n log m) algorithm for vlsi design rule checking," IEEE TCAD, vol. 11, no. 6, pp. 753--758, 1992.
[5]
G. E. Bier and A. R. Pleszkun, "An algorithm for design rule checking on a multiprocessor," in Proc. DAC, 1985, pp. 299--304.
[6]
F. Gregoretti and Z. Segall, "Analysis and evaluation of vlsi design rule checking implementation in a multiprocessor," in Proc. Int. Conf. Parallel Processing, 1984, pp. 7--14.
[7]
K.-T. Hsu, S. Sinha, Y.-C. Pi, C. Chiang, and T.-Y. Ho, "A distributed algorithm for layout geometry operations," in Proc. DAC, 2011, p. 182--187.
[8]
E. C. Carlson and R. A. Rutenbar, "Mask verification on the connection machine," in 25th ACM/IEEE, Design Automation Conference. Proceedings 1988. IEEE, 1988, pp. 134--140.
[9]
E. C. Carlson, "Design and performance evaluation of new massively parallel vlsi mask verification algorithms in jigsaw," in 27th ACM/IEEE Design Automation Conference. IEEE, 1990, pp. 253--259.
[10]
J. D. Marantz, "Exploiting parallelism in vlsi cad," Proc. IEEE ICCD'86, 1986.
[11]
K. MacPherson, "Parallel algorithms for layout verification," Master's thesis, Citeseer, 1995.
[12]
G. Guo, T.-W. Huang, Y. Lin, and M. Wong, "Gpu-accelerated path-based timing analysis," in 2021 58th ACM/IEEE Design Automation Conference (DAC). IEEE, 2021, pp. 721--726.
[13]
Y. Lin, Z. Jiang, J. Gu, W. Li, S. Dhar, H. Ren, B. Khailany, and D. Z. Pan, "Dreamplace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 4, pp. 748--761, 2020.
[14]
Y. Zhang, H. Ren, A. Sridharan, and B. Khailany, "Gatspi: Gpu accelerated gate-level simulation for power improvement," arXiv preprint arXiv:2203.06117, 2022.
[15]
S. Liu, P. Liao, R. Zhang, Z. Chen, W. Lv, Y. Lin, and B. Yu, "Fastgr: Global routing on cpu-gpu with heterogeneous task graph scheduler," IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), 2022.
[16]
T.-W. Huang, D.-L. Lin, C.-X. Lin, and Y. Lin, "Taskflow: A lightweight parallel and heterogeneous task graph computing system," IEEE Transactions on Parallel and Distributed Systems, vol. 33, no. 6, pp. 1303--1320, 2021.
[17]
Z. Guo, J. Mai, and Y. Lin, "Ultrafast cpu/gpu kernels for density accumulation in placement," in 2021 58th ACM/IEEE Design Automation Conference (DAC). IEEE, 2021, pp. 1123--1128.
[18]
S. Lin, J. Liu, and M. D. Wong, "Gamer: Gpu accelerated maze routing," in 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). IEEE, 2021, pp. 1--8.
[19]
Z. Guo, T.-W. Huang, and Y. Lin, "Gpu-accelerated static timing analysis," in Proceedings of the 39th International Conference on Computer-Aided Design, 2020, pp. 1--9.
[20]
Y. Lin, "Gpu acceleration in vlsi back-end design: Overview and case studies," in 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD). IEEE, 2020, pp. 1--4.
[21]
Y. Zhang, H. Ren, B. Keller, and B. Khailany, "Problem c: Gpu accelerated logic re-simulation," in Proceedings of the 39th International Conference on Computer-Aided Design, 2020, pp. 1--4.
[22]
G. Pasandi, S. Pratty, D. Brown, Y. Zhang, H. Ren, and B. Khailany, "2021 iccad cad contest problem c: Gpu accelerated logic rewriting," in 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). IEEE 2021, pp. 1--6.
[23]
"KLayout," https://klayout.de/.
[24]
J. JéJé, "An introduction to parallel algorithms," Reading, MA: Addison-Wesley, vol. 10, p. 133889, 1992.
[25]
M. I. Shamos and D. Hoey, "Geometric intersection problems," in 17th Annual Symposium on Foundations of Computer Science (sfcs 1976). IEEE, 1976, pp. 208--215.
[26]
Y. Sun and G. E. Blelloch, "Parallel range, segment and rectangle queries with augmented maps," in 2019 Proceedings of the Twenty-First Workshop on Algorithm Engineering and Experiments (ALENEX). SIAM, 2019, pp. 159--173.
[27]
T. Ajayi, V. A. Chhabria, M. Fogaça, S. Hashemi, A. Hosny, A. B. Kahng, M. Kim, J. Lee, U. Mallappa, M. Neseem et al., "Toward an open-source digital flow: First learnings from the openroad project," in Proc. DAC, 2019, pp. 1--4.

Cited By

View all
  • (2025)A Unified Parallel Framework for LUT Mapping and Logic OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.342907944:1(214-226)Online publication date: 1-Jan-2025
  • (2024)PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan GeometryProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3657367(1-6)Online publication date: 23-Jun-2024
  • (2024)Massively Parallel AIG ResubstitutionProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655987(1-6)Online publication date: 23-Jun-2024
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design
October 2022
1467 pages
ISBN:9781450392174
DOI:10.1145/3508352
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

In-Cooperation

  • IEEE-EDS: Electronic Devices Society
  • IEEE CAS
  • IEEE CEDA

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 December 2022

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Research-article

Conference

ICCAD '22
Sponsor:
ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design
October 30 - November 3, 2022
California, San Diego

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)55
  • Downloads (Last 6 weeks)4
Reflects downloads up to 28 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2025)A Unified Parallel Framework for LUT Mapping and Logic OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.342907944:1(214-226)Online publication date: 1-Jan-2025
  • (2024)PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan GeometryProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3657367(1-6)Online publication date: 23-Jun-2024
  • (2024)Massively Parallel AIG ResubstitutionProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655987(1-6)Online publication date: 23-Jun-2024
  • (2024)Performance-Driven Analog Layout Automation: Current Status and Future DirectionsProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473859(679-685)Online publication date: 22-Jan-2024
  • (2023)OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247734(1-6)Online publication date: 9-Jul-2023

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media