research-article

Multi-Package Co-Design for Chiplet Integration

Authors:

Tsung-Yi HoAuthors Info & Claims

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

Article No.: 114, Pages 1 - 9

https://doi.org/10.1145/3508352.3549404

Published: 22 December 2022 Publication History

Abstract

Due to the cost and design complexity associated with advanced technology nodes, it is difficult for traditional monolithic System-on-Chip to follow the Moore's Law, which means the economic benefits have been weakened. Semiconductor industries are looking for advanced packages to improve the economic advantages. Since the multi-chiplet architecture supporting heterogeneous integration has the robust re-usability and effective cost reduction, chiplet integration has become the mainstream of advanced packages. Nowadays, the number of mounted chiplets in a package is continuously increasing with the requirement of high system performance. However, the large area caused by the increasing of chiplets leads to the serious reliability issues, including warpage and bump stress, which worsens the yield and cost. The multi-package architecture, which can distribute chiplets to multiple packages and use less area of each package, is a popular alternative to enhance the reliability and reduce the cost in advanced packages. However, the primary challenge of the multi-package architecture lies in the tradeoff between the inter-package costs, i.e., the interconnection among packages, and the intra-package costs, i.e., the reliability caused by warpage and bump stress. Therefore, a co-design methodology is indispensable to optimize multiple packages simultaneously to improve the quality of the whole system. To tackle this challenge, we adopt mathematical programming methods in the multi-package co-design problem regarding the nature of the synergistic optimization of multiple packages. To the best of our knowledge, this is the first work to solve the multi-package co-design problem.

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Cited By

Chen SLi SZhuang ZZheng SLiang ZHo TYu BSangiovanni-Vincentelli A(2024)Floorplet: Performance-Aware Floorplan Framework for Chiplet IntegrationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334730243:6(1638-1649)Online publication date: 1-Jun-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3347302
Sangiovanni-Vincentelli ALiang ZZhou ZZhang JChinnery DHui-Ru Jiang I(2023)Automated Design of ChipletsProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3578917(1-8)Online publication date: 26-Mar-2023
https://dl.acm.org/doi/10.1145/3569052.3578917
Zhu QCao YQiu YGao XYin WWang L(2023)A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications2023 International Conference on Field Programmable Technology (ICFPT)10.1109/ICFPT59805.2023.00054(298-299)Online publication date: 12-Dec-2023
https://doi.org/10.1109/ICFPT59805.2023.00054

Index Terms

Multi-Package Co-Design for Chiplet Integration
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
2. Hardware

Index terms have been assigned to the content through auto-classification.

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cover image ACM Conferences

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

October 2022

1467 pages

ISBN:9781450392174

DOI:10.1145/3508352

Conference Chair:
Tulika Mitra
National University of Singapore
,
Program Chairs:
Evangeline Young
The Chinese University of Hong Kong
,
Jinjun Xiong
University at Buffalo (UB)

Copyright © 2022 ACM.

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Published: 22 December 2022

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ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design

October 30 - November 3, 2022

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Cited By

Chen SLi SZhuang ZZheng SLiang ZHo TYu BSangiovanni-Vincentelli A(2024)Floorplet: Performance-Aware Floorplan Framework for Chiplet IntegrationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334730243:6(1638-1649)Online publication date: 1-Jun-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3347302
Sangiovanni-Vincentelli ALiang ZZhou ZZhang JChinnery DHui-Ru Jiang I(2023)Automated Design of ChipletsProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3578917(1-8)Online publication date: 26-Mar-2023
https://dl.acm.org/doi/10.1145/3569052.3578917
Zhu QCao YQiu YGao XYin WWang L(2023)A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications2023 International Conference on Field Programmable Technology (ICFPT)10.1109/ICFPT59805.2023.00054(298-299)Online publication date: 12-Dec-2023
https://doi.org/10.1109/ICFPT59805.2023.00054

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