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View all- Chang YHui-Ru Jiang IPosser G(2024)Physical Design Challenges in Modern Heterogeneous IntegrationProceedings of the 2024 International Symposium on Physical Design10.1145/3626184.3639690(125-134)Online publication date: 12-Mar-2024
In modern advanced packaging, redistribution layers (RDLs) are often used for signal transmission among chips, and vias are used for communication among different layers. Most existing RDL routers perform via planning before routing. However, since vias ...
In today's VLSI designs, there can be many blockages in a routing region. The obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem has become an important problem in the physical design stage of VLSI circuits. This problem has attracted a ...
The flip-chip packaging is introduced for modern IC designs with higher integration density and larger I/O counts. It is necessary to consider routing obstacles for modern flip-chip designs, where the obstacles could be regions blocked for signal ...
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