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Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion

Published: 22 December 2022 Publication History

Abstract

Although compute-in-memory (CIM) is considered as one of the promising solutions to overcome memory wall problem, the variations in analog voltage computation and analog-to-digital-converter (ADC) cost still remain as design challenges. In this paper, we present a 7T SRAM CIM that seamlessly supports multiply-accumulation (MAC) operation between 4-bit inputs and 8-bit weights. In the proposed CIM, highly parallel and robust MAC operations are enabled by exploiting the bit-line charge-sharing scheme to simultaneously process multiple inputs. For the readout of analog MAC values, instead of adopting the conventional ADC structure, the bit-line charge-sharing is efficiently used to reduce the implementation cost of the reference voltage generations. Based on the in-SRAM reference voltage generation and the parallel analog readout in all columns, the proposed CIM efficiently reduces ADC power and area cost. In addition, the variation models from Monte-Carlo simulations are also used during training to reduce the accuracy drop due to process variations. The implementation of 256×64 7T SRAM CIM using 28nm CMOS process shows that it operates in the wide voltage range from 0.6V to 1.2V with energy efficiency of 45.8-TOPS/W at 0.6V.

References

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Cited By

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  • (2024)Comprehensive Analysis of Read Fluctuations in ReRAM CiM by Using Fluctuation Pattern ClassifierIEICE Transactions on Electronics10.1587/transele.2023CTP0002E107.C:10(416-425)Online publication date: 1-Oct-2024
  • (2024)OSA-HCIM: On-the-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision ConfigurationProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473966(539-544)Online publication date: 22-Jan-2024
  • (2024)An XOR-10T SRAM computing-in-memory macro with current MAC operations and time-to-digital conversion for BNN edge processorsAEU - International Journal of Electronics and Communications10.1016/j.aeue.2024.155346182(155346)Online publication date: Jul-2024

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              cover image ACM Conferences
              ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design
              October 2022
              1467 pages
              ISBN:9781450392174
              DOI:10.1145/3508352
              Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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              Publication History

              Published: 22 December 2022

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              Author Tags

              1. In-SRAM reference voltage generation
              2. SRAM
              3. compute-in-memory (CIM)
              4. variation-aware training

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              ICCAD '22
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              ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design
              October 30 - November 3, 2022
              California, San Diego

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              Cited By

              View all
              • (2024)Comprehensive Analysis of Read Fluctuations in ReRAM CiM by Using Fluctuation Pattern ClassifierIEICE Transactions on Electronics10.1587/transele.2023CTP0002E107.C:10(416-425)Online publication date: 1-Oct-2024
              • (2024)OSA-HCIM: On-the-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision ConfigurationProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473966(539-544)Online publication date: 22-Jan-2024
              • (2024)An XOR-10T SRAM computing-in-memory macro with current MAC operations and time-to-digital conversion for BNN edge processorsAEU - International Journal of Electronics and Communications10.1016/j.aeue.2024.155346182(155346)Online publication date: Jul-2024

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