research-article

ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication

Authors:

Ebadollah Taheri,

Sudeep Pasricha,

Mahdi NikdastAuthors Info & Claims

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

Article No.: 24, Pages 1 - 9

https://doi.org/10.1145/3508352.3549432

Published: 22 December 2022 Publication History

Abstract

2.5D chiplet systems have been proposed to improve the low manufacturing yield of large-scale chips. However, connecting the chiplets through an electronic interposer imposes a high traffic load on the interposer network. Silicon photonics technology has shown great promise towards handling a high volume of traffic with low latency in intra-chip network-on-chip (NoC) fabrics. Although recent advances in silicon photonic devices have extended photonic NoCs to enable high bandwidth communication in 2.5D chiplet systems, such interposer-based photonic networks still suffer from high power consumption. In this work, we design and analyze a novel Reconfigurable power-efficient and congestion-aware Silicon-Photonic 2.5D Interposer network, called ReSiPI. Considering runtime traffic, ReSiPI is able to dynamically deploy inter-chiplet photonic gateways to improve the overall network congestion. ReSiPI also employs switching elements based on phase change materials (PCMs) to dynamically reconfigure and power-gate the photonic interposer network, thereby improving the network power efficiency. Compared to the best prior state-of-the-art 2.5D photonic network, ReSiPI demonstrates, on average, 37% lower latency, 25% power reduction, and 53% energy minimization in the network.

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Cited By

Zhang HZhang HHuang ZChen Y(2025)ChipAI: A scalable chiplet-based accelerator for efficient DNN inference using silicon photonicsJournal of Systems Architecture10.1016/j.sysarc.2024.103308158(103308)Online publication date: Jan-2025
https://doi.org/10.1016/j.sysarc.2024.103308
Sunny FShafiee ACharbonnier BNikdast MPasricha S(2024)COMET: A Cross-Layer Optimized Optical Phase-Change Main Memory Architecture2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546876(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546876
Sunny FTaheri ENikdast MPasricha S(2024)Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators2024 IEEE 42nd VLSI Test Symposium (VTS)10.1109/VTS60656.2024.10538500(1-4)Online publication date: 22-Apr-2024
https://doi.org/10.1109/VTS60656.2024.10538500
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Index Terms

ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
2. Hardware

Index terms have been assigned to the content through auto-classification.

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cover image ACM Conferences

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

October 2022

1467 pages

ISBN:9781450392174

DOI:10.1145/3508352

Conference Chair:
Tulika Mitra
National University of Singapore
,
Program Chairs:
Evangeline Young
The Chinese University of Hong Kong
,
Jinjun Xiong
University at Buffalo (UB)

Copyright © 2022 ACM.

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Published: 22 December 2022

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National Science Foundation (NSF)

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ICCAD '22

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ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design

October 30 - November 3, 2022

California, San Diego

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Cited By

Zhang HZhang HHuang ZChen Y(2025)ChipAI: A scalable chiplet-based accelerator for efficient DNN inference using silicon photonicsJournal of Systems Architecture10.1016/j.sysarc.2024.103308158(103308)Online publication date: Jan-2025
https://doi.org/10.1016/j.sysarc.2024.103308
Sunny FShafiee ACharbonnier BNikdast MPasricha S(2024)COMET: A Cross-Layer Optimized Optical Phase-Change Main Memory Architecture2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546876(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546876
Sunny FTaheri ENikdast MPasricha S(2024)Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators2024 IEEE 42nd VLSI Test Symposium (VTS)10.1109/VTS60656.2024.10538500(1-4)Online publication date: 22-Apr-2024
https://doi.org/10.1109/VTS60656.2024.10538500
Taheri EPasricha SNikdast M(2024)ReD: A Reliable and Deadlock-Free Routing for 2.5-D Chiplet-Based Interposer NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.339966043:12(4599-4612)Online publication date: 1-Dec-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3399660
Sunny FTaheri ENikdast MPasricha S(2023)Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137317(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137317
Li GYe Y(2023)HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332882843:3(812-825)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3328828
Taheri EKim RNikdast M(2023)AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-ChipIEEE Transactions on Computers10.1109/TC.2023.324826072:8(2278-2292)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TC.2023.3248260
Zohrei SAlsalem BBeux S(2023)A Method to Reduce the Design Complexity of Nanophotonic Interconnects2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)10.1109/NEWCAS57931.2023.10198144(1-5)Online publication date: 26-Jun-2023
https://doi.org/10.1109/NEWCAS57931.2023.10198144
Shafiee APasricha SNikdast M(2023)A Survey on Optical Phase-Change Memory: The Promise and ChallengesIEEE Access10.1109/ACCESS.2023.324114611(11781-11803)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3241146

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