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Dynamic Frequency Boosting Beyond Critical Path Delay

Published: 22 December 2022 Publication History

Abstract

This paper introduces an innovative post-implementation Dynamic Frequency Boosting (DFB) technique to release "hidden" performance margins of digital circuit designs currently suppressed by typical critical path constraint design flows, thus defining higher limits of operation speed. The proposed technique goes beyond state-of-the-art and exploits the data-driven path delay variability incorporating an innovative hardware clocking mechanism that detects in real-time the paths' activation. In contrast to timing speculation, the operating speed is adjusted on the nominal path delay activation, succeeding an error-free acceleration. The proposed technique has been evaluated on three FPGA-based use cases carefully selected to exhibit differing domain characteristics, i.e i) a third party DNN inference accelerator IP for CIFAR-10 images achieving an average speedup of 18%, ii) a highly designer-optimized Optical Digital Equalizer design, in which DBF delivered a speedup of 50% and iii) a set of 5 synthetic designs examining high frequency (beyond 400 MHz) applications in FPGAs, achieving accelerations of 20--60% depending on the underlying path variability.

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cover image ACM Conferences
ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design
October 2022
1467 pages
ISBN:9781450392174
DOI:10.1145/3508352
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • IEEE-EDS: Electronic Devices Society
  • IEEE CAS
  • IEEE CEDA

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Association for Computing Machinery

New York, NY, United States

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Published: 22 December 2022

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Author Tags

  1. EDA
  2. FPGA
  3. IC
  4. boosting
  5. clock
  6. critical path
  7. delay
  8. design
  9. dynamic
  10. frequency
  11. slack
  12. synchronous
  13. timing
  14. variability

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ICCAD '22
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ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design
October 30 - November 3, 2022
California, San Diego

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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