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Designing Energy-Efficient Decision Tree Memristor Crossbar Circuits Using Binary Classification Graphs

Published: 22 December 2022 Publication History

Abstract

We propose a method to design in-memory, energy-efficient, and compact memristor crossbar circuits for implementing decision trees using flow-based computing. We develop a new tool called binary classification graph, which is equivalent to decision trees in accuracy but uses bit values of input features to make decisions instead of thresholds. Our proposed design is resilient to manufacturing errors and can scale to large crossbar sizes due to the utilization of sneak paths in computations. Our design uses zero transistor and one memristor (0T1R) crossbars with only two resistance states of high and low, which makes it resilient to resistance drift and radiation degradation. We test the performance of our designs on multiple standard machine learning datasets and show that our method utilizes circuits of size 5.23 × 10-3 mm2 and uses 20.5 pJ per decision, and outperforms state-of-the-art decision tree acceleration algorithms on these metrics.

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  • (2024)Designing Energy-Efficient PATH-based Decision Tree Memristor Crossbar Circuits2024 IEEE 24th International Conference on Nanotechnology (NANO)10.1109/NANO61778.2024.10628690(209-213)Online publication date: 8-Jul-2024

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              cover image ACM Conferences
              ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design
              October 2022
              1467 pages
              ISBN:9781450392174
              DOI:10.1145/3508352
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              Published: 22 December 2022

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              • (2024)Designing Energy-Efficient PATH-based Decision Tree Memristor Crossbar Circuits2024 IEEE 24th International Conference on Nanotechnology (NANO)10.1109/NANO61778.2024.10628690(209-213)Online publication date: 8-Jul-2024

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