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Polynomial Formal Verification: Ensuring Correctness under Resource Constraints

Authors:

Rolf Drechsler,

Alireza MahzoonAuthors Info & Claims

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

Article No.: 70, Pages 1 - 9

https://doi.org/10.1145/3508352.3561104

Published: 22 December 2022 Publication History

Abstract

Recently, a lot of effort has been put into developing formal verification approaches by both academic and industrial research. In practice, these techniques often give satisfying results for some types of circuits, while they fail for others. A major challenge in this domain is that the verification techniques suffer from unpredictability in their performance. The only way to overcome this challenge is the calculation of bounds for the space and time complexities. If a verification method has polynomial space and time complexities, scalability can be guaranteed.

In this tutorial paper, we review recent developments in formal verification techniques and give a comprehensive overview of Polynomial Formal Verification (PFV). In PFV, polynomial upper bounds for the run-time and memory needed during the entire verification task hold. Thus, correctness under resource constraints can be ensured. We discuss the importance and advantages of PFV in the design flow. Formal methods on the bit-level and the word-level, and their complexities when used to verify different types of circuits, like adders, multipliers, or ALUs are presented. The current status of this new research field and directions for future work are discussed.

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Cited By

Schnieber MDrechsler R(2025)Automated polynomial formal verification using generalized binary decision diagram patternsPhilosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences10.1098/rsta.2023.0390383:2288Online publication date: 16-Jan-2025
https://doi.org/10.1098/rsta.2023.0390
Dominik CDrechsler R(2024)Polynomial Formal Verification of Sequential Circuits2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546775(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546775
Qayyum KKole ADatta KHassan MDrechsler R(2024)Exploring the Potential of Decision Diagrams for Efficient In-Memory Design VerificationProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658766(502-506)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658766
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Index Terms

Polynomial Formal Verification: Ensuring Correctness under Resource Constraints
1. Hardware
  1. Hardware validation
    1. Functional verification

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cover image ACM Conferences

ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

October 2022

1467 pages

ISBN:9781450392174

DOI:10.1145/3508352

Conference Chair:
Tulika Mitra
National University of Singapore
,
Program Chairs:
Evangeline Young
The Chinese University of Hong Kong
,
Jinjun Xiong
University at Buffalo (UB)

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Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Published: 22 December 2022

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October 30 - November 3, 2022

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Cited By

Schnieber MDrechsler R(2025)Automated polynomial formal verification using generalized binary decision diagram patternsPhilosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences10.1098/rsta.2023.0390383:2288Online publication date: 16-Jan-2025
https://doi.org/10.1098/rsta.2023.0390
Dominik CDrechsler R(2024)Polynomial Formal Verification of Sequential Circuits2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546775(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546775
Qayyum KKole ADatta KHassan MDrechsler R(2024)Exploring the Potential of Decision Diagrams for Efficient In-Memory Design VerificationProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658766(502-506)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658766
Nadeem MDrechsler R(2024)Polynomial Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures2024 IEEE 54th International Symposium on Multiple-Valued Logic (ISMVL)10.1109/ISMVL60454.2024.00037(149-154)Online publication date: 28-May-2024
https://doi.org/10.1109/ISMVL60454.2024.00037
Kleinekathöfer JMahzoon ADrechsler R(2023)Polynomial Formal Verification of Floating Point Adders2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137166(1-2)Online publication date: Apr-2023
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Drechsler RMahzoon A(2023)Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137149(1-2)Online publication date: Apr-2023
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Drechsler RSchnieber MZhu Qvon Hanxleden RStephen EBrandt J(2023)Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal VerificationProceedings of the 21st ACM-IEEE International Conference on Formal Methods and Models for System Design10.1145/3610579.3612941(122-125)Online publication date: 21-Sep-2023
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Weingarten LMahzoon AGoli MDrechsler R(2023)Polynomial Formal Verification of a Processor: A RISC-V Case Study2023 24th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED57927.2023.10129397(1-7)Online publication date: 5-Apr-2023
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