skip to main content
10.1145/3526241.3530327acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
research-article

SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories

Authors Info & Claims
Published:06 June 2022Publication History

ABSTRACT

Hybrid memory systems with a combination of DRAM and Non-Volatile Memory (NVM) types can make use of scalability and performance of both NVM and DRAM. Random placement of pages in Phase Change Memory (PCM) with more write accesses incurs higher write latencies. So, migrating write intensive pages from PCM to DRAM helps to reduce execution time and memory response time for applications. Existing techniques mainly focus on selecting the page migration candidate and migrate it immediately when it becomes eligible. This direct migration approach can hamper the response time of regular memory accesses. So, in our paper, we identify migration candidates and in addition, schedule when they can be migrated to DRAM. To realize this, we have used Selection and Run-time Scheduling of page Migration (SRS-Mig), a frame-based scheduling approach for migrations and read/write requests. SRS-Mig reduces migration overhead and guarantees future accesses to migrated pages to yield an improved execution time and memory response time for the applications. Experimental evaluation shows 30% improvement in execution time; 26% improvement memory response time, and considerable energy savings with the existing baseline techniques.

Skip Supplemental Material Section

Supplemental Material

GLSVLSI22-fp121.mp4

mp4

46 MB

References

  1. Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R Hower, Tushar Krishna, Somayeh Sardashti, et al . 2011. The gem5 simulator. ACM SIGARCH computer architecture news 39, 2 (2011), 1--7.Google ScholarGoogle Scholar
  2. Xianzhang Chen, Edwin H-M Sha, Weiwen Jiang, Qingfeng Zhuge, Junxi Chen, Jiejie Qin, and Yuansong Zeng. 2016. The design of an efficient swap mechanism for hybrid DRAM-NVM systems. In 2016 International Conference on Embedded Software (EMSOFT). IEEE, 1--10.Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. John L Henning. 2006. SPEC CPU2006 benchmark descriptions. ACM SIGARCH Computer Architecture News 34, 4 (2006), 1--17.Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. Mahzabeen Islam, Shashank Adavally, Marko Scrbak, and Krishna Kavi. 2020. On-the-fly page migration and address reconciliation for heterogeneous memory systems. ACM Journal on Emerging Technologies in Computing Systems (JETC) 16, 1 (2020), 1--27.Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Soyoon Lee, Hyokyung Bahn, and Sam H Noh. 2013. CLOCK-DWF: A write-history-aware page replacement algorithm for hybrid PCM and DRAM memory architectures. IEEE Trans. Comput. 63, 9 (2013), 2187--2200.Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Jack A Mandelman, Robert H Dennard, Gary B Bronner, John K DeBrosse, Rama Divakaruni, Yujun Li, and Carl J Radens. 2002. Challenges and future directions for the scaling of dynamic random-access memory (DRAM). IBM Journal of Research and Development 46, 2.3 (2002), 187--212.Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Justin Meza, Jichuan Chang, HanBin Yoon, Onur Mutlu, and Parthasarathy Ranganathan. 2012. Enabling efficient and scalable hybrid memories using fine-granularity DRAM cache management. IEEE Computer Architecture Letters 11, 2 (2012), 61--64.Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. Sparsh Mittal. 2012. A survey of architectural techniques for DRAM power management. International Journal of High Performance Systems Architecture 4, 2 (2012), 110--119.Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Onur Mutlu and Lavanya Subramanian. 2014. Research problems and opportunities in memory systems. Supercomputing frontiers and innovations 1, 3 (2014), 19--55.Google ScholarGoogle Scholar
  10. Matthew Poremba, Tao Zhang, and Yuan Xie. 2015. Nvmain 2.0: A user-friendly memory simulator to model (non-) volatile memory systems. IEEE Computer Architecture Letters 14, 2 (2015), 140--143.Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Moinuddin K Qureshi, Vijayalakshmi Srinivasan, and Jude A Rivers. 2009. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the 36th annual international symposium on Computer architecture. 24--33.Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. Luiz E Ramos, Eugene Gorbatov, and Ricardo Bianchini. 2011. Page placement in hybrid memory systems. In Proceedings of the international conference on Supercomputing. 85--95.Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Simone Raoux, Feng Xiong, Matthias Wuttig, and Eric Pop. 2014. Phase change materials and phase change memory. MRS bulletin 39, 8 (2014), 703--710.Google ScholarGoogle Scholar
  14. Reza Salkhordeh and Hossein Asadi. 2016. An operating system level data migration scheme in hybrid DRAM-NVM memory architecture. In 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 936--941.Google ScholarGoogle Scholar
  15. Yujuan Tan, Baiping Wang, Zhichao Yan, Qiuwei Deng, Xianzhang Chen, and Duo Liu. 2019. Uimigrate: Adaptive data migration for hybrid non-volatile memory systems. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 860--865.Google ScholarGoogle Scholar
  16. Jeffrey S Vetter and Sparsh Mittal. 2015. Opportunities for nonvolatile memory systems in extreme-scale high-performance computing. Computing in Science & Engineering 17, 2 (2015), 73--82.Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. Wei Wei, Dejun Jiang, Sally A McKee, Jin Xiong, and Mingyu Chen. 2015. Exploiting program semantics to place data in hybrid memory. In 2015 International Conference on Parallel Architecture and Compilation (PACT). IEEE, 163--173.Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. Panruo Wu, Dong Li, Zizhong Chen, Jeffrey S Vetter, and Sparsh Mittal. 2016. Algorithm-directed data placement in explicitly managed non-volatile memory. In Proceedings of the 25th ACM International Symposium on High-Performance Parallel and Distributed Computing. 141--152.Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael A Harding, and Onur Mutlu. 2012. Row buffer locality aware caching policies for hybrid memories. In 2012 IEEE 30th International Conference on Computer Design (ICCD). IEEE, 337--344.Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories

        Recommendations

        Comments

        Login options

        Check if you have access through your login credentials or your institution to get full access on this article.

        Sign in
        • Published in

          cover image ACM Conferences
          GLSVLSI '22: Proceedings of the Great Lakes Symposium on VLSI 2022
          June 2022
          560 pages
          ISBN:9781450393225
          DOI:10.1145/3526241

          Copyright © 2022 ACM

          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

          Publisher

          Association for Computing Machinery

          New York, NY, United States

          Publication History

          • Published: 6 June 2022

          Permissions

          Request permissions about this article.

          Request Permissions

          Check for updates

          Qualifiers

          • research-article

          Acceptance Rates

          Overall Acceptance Rate312of1,156submissions,27%

          Upcoming Conference

          GLSVLSI '24
          Great Lakes Symposium on VLSI 2024
          June 12 - 14, 2024
          Clearwater , FL , USA
        • Article Metrics

          • Downloads (Last 12 months)36
          • Downloads (Last 6 weeks)12

          Other Metrics

        PDF Format

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader