research-article

Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance

Authors:

Dimitrios Garyfallou,

Anastasis Vagenas,

Charalampos Antoniadis,

George StamoulisAuthors Info & Claims

GLSVLSI '22: Proceedings of the Great Lakes Symposium on VLSI 2022

Pages 77 - 83

https://doi.org/10.1145/3526241.3530343

Published: 06 June 2022 Publication History

Abstract

With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ramps, while gate-interconnect interdependencies are stronger. Moreover, efficiency is a serious concern since repeatedly invoking a signoff tool during incremental optimization of modern VLSI circuits has become a major bottleneck. In this paper, we introduce a novel machine learning approach for timing estimation of gate-level stages using current source models and the concept of multiple slew and effective capacitance values. First, we exploit a fast iterative algorithm for initial stage timing estimation and feature extraction, and then we employ four artificial neural networks to correlate the initial delay and slew estimates for both the driver and interconnect with golden SPICE results. Contrary to prior works, our method uses fewer and more accurate features to represent the stage, leading to more efficient models. Experimental evaluation on driver-interconnect stages implemented in 7 nm FinFET technology indicates that our method leads to 0.99% (0.90 ps) and 2.54% (2.59 ps) mean error against SPICE for stage delay and slew, respectively. Furthermore, it has a small memory footprint (1.27 MB) and performs 35× faster than a commercial signoff tool. Thus, it may be integrated into timing-driven optimization steps to provide signoff accuracy and expedite timing closure.

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Bai TDeng ZCao PAmrouch HHu JGarg SLin Y(2024)Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active LearningProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685965(1-7)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685965
Lin SGuo GHuang TSheng WYoung EWong MDe V(2024)GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing AnalysisProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655983(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3655983
Hyun DJung YShin Y(2024)Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural NetworkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331699143:1(244-248)Online publication date: Jan-2024
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Index Terms

Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
1. Computing methodologies
  1. Machine learning
2. Hardware
  1. Electronic design automation
    1. Timing analysis

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cover image ACM Conferences

GLSVLSI '22: Proceedings of the Great Lakes Symposium on VLSI 2022

June 2022

560 pages

ISBN:9781450393225

DOI:10.1145/3526241

General Chairs:
Ioannis Savidis
Drexel University, USA
,
Avesta Sasan
University of California, Davis, USA
,
Program Chairs:
Himanshu Thapliyal
University of Tennessee, Knoxville, USA
,
Ronald F. DeMara
University of Central Florida, USA

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

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Published: 06 June 2022

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European Regional Development Fund (ERDF) and Greek national funds - Operational Program EPAnEK - call RESEARCH-CREATE-INNOVATE

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GLSVLSI '22

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GLSVLSI '22: Great Lakes Symposium on VLSI 2022

June 6 - 8, 2022

CA, Irvine, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Great Lakes Symposium on VLSI 2025

June 30 - July 2, 2025

New Orleans , LA , USA

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Cited By

Bai TDeng ZCao PAmrouch HHu JGarg SLin Y(2024)Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active LearningProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685965(1-7)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685965
Lin SGuo GHuang TSheng WYoung EWong MDe V(2024)GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing AnalysisProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655983(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3655983
Hyun DJung YShin Y(2024)Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural NetworkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331699143:1(244-248)Online publication date: Jan-2024
https://doi.org/10.1109/TCAD.2023.3316991
Vagenas AGaryfallou DEvmorfopoulos NStamoulis G(2024)A learning-based method for performance optimization of timing analysis2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD61181.2024.10745408(1-4)Online publication date: 2-Jul-2024
https://doi.org/10.1109/SMACD61181.2024.10745408
Bai TDeng ZCao P(2024)Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active Learning2024 ACM/IEEE 6th Symposium on Machine Learning for CAD (MLCAD)10.1109/MLCAD62225.2024.10740261(1-7)Online publication date: 9-Sep-2024
https://doi.org/10.1109/MLCAD62225.2024.10740261
Zha PGuo JZhang S(2024)Stage Delay Calculation Method Considering Effective Capacitance2024 7th International Conference on Electronics Technology (ICET)10.1109/ICET61945.2024.10673389(74-79)Online publication date: 17-May-2024
https://doi.org/10.1109/ICET61945.2024.10673389
Guo XZhu LCai Y(2024)Harnessing Graph Learning for Efficient Timing SignoffAI-Enabled Electronic Circuit and System Design10.1007/978-3-031-71436-8_5(155-187)Online publication date: 17-Oct-2024
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Chatzimichail AAntoniadis CBellas NMassoud Y(2023)Low Power Hardware Architecture for Sampling-free Bayesian Neural Networks inference2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10181925(1-5)Online publication date: 21-May-2023
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Paliaroutis GTsoumanis PGaryfallou DVagenas AEvmorfopoulos NStamoulis G(2023)Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT59622.2023.10313573(1-6)Online publication date: 3-Oct-2023
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Zhu LGu YGuo X(2023)RC-GNN: Fast and Accurate Signoff Wire Delay Estimation with Customized Graph Neural Networks2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)10.1109/AICAS57966.2023.10168562(1-5)Online publication date: 11-Jun-2023
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