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SODA-OPT an MLIR based flow for co-design and high-level synthesis

Published: 17 May 2022 Publication History

Abstract

Due to technology and power limitations, general-purpose processing units are experiencing progressively smaller performance gains. Computer architecture innovations are essential to keep performance steadily increasing. Thus domain-specific accelerators are receiving renewed interest and have shown to benefit different scientific and machine learning applications [1, 3]. High-Level-Synthesis (HLS) provides a way to quickly generate hardware descriptions for domain-specific accelerators starting from high-level applications. However, state-of-the-art tools typically require the application to be manually translated to C/C++ and carefully annotated to improve final design performance. This cumbersome process prevents scientists and researchers from tapping into the power of HLS, as many of their applications require significant effort to be ported.

References

[1]
J. Appleyard and S. Yokim. 2017. Programming Tensor Cores in CUDA 9. https://developer.nvidia.com/blog/programming-tensor-cores-cuda-9/
[2]
F. Ferrandi, V. G. Castellana, S. Curzel, P. Fezzardi, M. Fiorito, M. Lattuada, M. Minutoli, C. Pilato, and A. Tumeo. 2021. Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications. In DAC. ACM, 1327--1330.
[3]
N.P. Jouppi, C. Young, N. Patil, D. Patterson, G. Agrawal, R. Bajwa, S. Bates, S. Bhatia, N. Boden, A. Borchers, et al. 2017. In-datacenter performance analysis of a tensor processing unit. In ISCA. ACM, 1--12.
[4]
C. Lattner, M. Amini, U. Bondhugula, A. Cohen, A. Davis, J. Pienaar, R. Riddle, T. Shpeisman, N. Vasilache, and O. Zinenko. 2021. MLIR: Scaling compiler infrastructure for domain specific computation. In CGO. ACM, 2--14.
[5]
Pouchet, L. and others. 2021. PolyBench/C 4.2.1. https://web.cse.ohio-state.edu/~pouchet.2/software/polybench/

Cited By

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  • (2024)HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/366347729:5(1-23)Online publication date: 3-May-2024
  • (2024)A Systematic Translation Validation Framework for MLIR-Based CompilersInternational Journal of Software Engineering and Knowledge Engineering10.1142/S021819402450030X34:10(1621-1640)Online publication date: 19-Jul-2024
  • (2023)Analysis and Implementation of Space Avionics Co-Processor for Deep Learning Acceleration2023 European Data Handling & Data Processing Conference (EDHPC)10.23919/EDHPC59100.2023.10396469(1-8)Online publication date: 2-Oct-2023
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cover image ACM Conferences
CF '22: Proceedings of the 19th ACM International Conference on Computing Frontiers
May 2022
321 pages
ISBN:9781450393386
DOI:10.1145/3528416
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Publication History

Published: 17 May 2022

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Author Tags

  1. HLS
  2. HW/SW partitioning
  3. MLIR
  4. compiler optimizations

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View all
  • (2024)HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/366347729:5(1-23)Online publication date: 3-May-2024
  • (2024)A Systematic Translation Validation Framework for MLIR-Based CompilersInternational Journal of Software Engineering and Knowledge Engineering10.1142/S021819402450030X34:10(1621-1640)Online publication date: 19-Jul-2024
  • (2023)Analysis and Implementation of Space Avionics Co-Processor for Deep Learning Acceleration2023 European Data Handling & Data Processing Conference (EDHPC)10.23919/EDHPC59100.2023.10396469(1-8)Online publication date: 2-Oct-2023
  • (2023)Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGAProceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis10.1145/3624062.3624543(556-565)Online publication date: 12-Nov-2023
  • (2023)Preserving Privacy of Neuromorphic Hardware From PCIe Congestion Side-Channel Attack2023 IEEE 47th Annual Computers, Software, and Applications Conference (COMPSAC)10.1109/COMPSAC57700.2023.00094(689-698)Online publication date: Jun-2023

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