research-article

A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node

Authors:

Jaehoon Jeong,

Jonghyun Ko,

Taigon SongAuthors Info & Claims

ISLPED '22: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

Article No.: 16, Pages 1 - 6

https://doi.org/10.1145/3531437.3539707

Published: 01 August 2022 Publication History

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ISLPED '22: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node

Pages 1 - 6

Abstract
References

Abstract

Nanosheet FETs (NSFETs) are expected to be the post-FinFET device in the technology nodes of 5 nm and beyond. However, despite the high potential of NSFETs, few studies report the impact of NSFETs in the digital VLSI’s perspective. In this paper, we present a study of NSFETs for the optimal standard cell (SDC) library design and pin accessibility-aware layout for less routing congestion and low power consumption. For this objective, we present five novel methodologies to tackle the pin accessibility issues that rise in SDC designs in extremely-low routing resource environments (4 tracks) and emphasize the importance of local trench contact (LTC) in it. Using our methodology, we improve design metrics such as power consumption, total area, and wirelength by -11.0%, -13.2%, and 16.0%, respectively. By our study, we expect the routing congestion issues that additionally occur in advanced technology nodes to be handled and better full-chip designs to be done in 3 nm and beyond.

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Cited By

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Wang PTon KLin R(2024)Routing Intent Aware Pin Access Point Selection for Standard Cell Designs2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528690(1-8)Online publication date: 3-Apr-2024
https://doi.org/10.1109/ISQED60706.2024.10528690
Jeong JShin YLee HKo JKim JSong T(2024)Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm NodeIEEE Access10.1109/ACCESS.2024.342733212(97557-97571)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3427332
Lee JLee JPark SKang S(2023)Multi-Source Transfer Learning for Design Technology Co-Optimization2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED58423.2023.10244484(1-6)Online publication date: 7-Aug-2023
https://doi.org/10.1109/ISLPED58423.2023.10244484

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Published In

ISLPED '22: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

August 2022

192 pages

ISBN:9781450393546

DOI:10.1145/3531437

Editors:
Helen Li
Duke University
,
Charles Augustine
Intel
,
Ayse Kivilcim Coskun
Boston University
,
Swaroop Ghosh
Penn State University

© 2022 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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New York, NY, United States

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Published: 01 August 2022

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ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design

August 1 - 3, 2022

MA, Boston, USA

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Wang PTon KLin R(2024)Routing Intent Aware Pin Access Point Selection for Standard Cell Designs2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528690(1-8)Online publication date: 3-Apr-2024
https://doi.org/10.1109/ISQED60706.2024.10528690
Jeong JShin YLee HKo JKim JSong T(2024)Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm NodeIEEE Access10.1109/ACCESS.2024.342733212(97557-97571)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3427332
Lee JLee JPark SKang S(2023)Multi-Source Transfer Learning for Design Technology Co-Optimization2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED58423.2023.10244484(1-6)Online publication date: 7-Aug-2023
https://doi.org/10.1109/ISLPED58423.2023.10244484

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Abstract

References

Cited By

Recommendations

Pin Accessibility-Driven Detailed Placement Refinement

Simulation of 2D ReS2/WSe2 based complementary field-effect transistors towards 1 nm technology node

Improving Detailed Routability and Pin Access with 3D Monolithic Standard Cells

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Simulation of 2D ReS₂/WSe₂ based complementary field-effect transistors towards 1 nm technology node