survey

Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAs

Authors:

Emanuele Del Sozzo,

Davide Conficconi,

Donatella Sciuto,

Marco D. SantambrogioAuthors Info & Claims

ACM Computing Surveys, Volume 55, Issue 5

Article No.: 106, Pages 1 - 48

https://doi.org/10.1145/3532989

Published: 03 December 2022 Publication History

Abstract

Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications, embedded, and an emerging alternative for cloud-scale acceleration. However, FPGA adoption found limitations in their programmability and required knowledge. Therefore, researchers focused on FPGA abstractions and automation tools. Here, we survey three leading digital design abstractions: Hardware Description Languages (HDLs), High-Level Synthesis (HLS) tools, and Domain-Specific Languages (DSLs). We review these abstraction solutions, provide a timeline, and propose a taxonomy for each abstraction trend: programming models for HDLs; Intellectual Property (IP)-based or System-based toolchains for HLS; application, architecture, and infrastructure domains for DSLs.

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cover image ACM Computing Surveys

ACM Computing Surveys Volume 55, Issue 5

May 2023

810 pages

ISSN:0360-0300

EISSN:1557-7341

DOI:10.1145/3567470

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Published: 03 December 2022

Online AM: 27 April 2022

Accepted: 06 April 2022

Revised: 22 February 2022

Received: 31 July 2021

Published in CSUR Volume 55, Issue 5

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Lahti SHämäläinen T(2025)High-Level Synthesis for FPGAs—A Hardware Engineer’s PerspectiveIEEE Access10.1109/ACCESS.2025.354032013(28574-28593)Online publication date: 2025
https://doi.org/10.1109/ACCESS.2025.3540320
Nieto RMachado FFernández-Conde JLobato DCañas J(2025)Open-source ROS-based simulation for verification of FPGA robotics applicationsMicroprocessors and Microsystems10.1016/j.micpro.2025.105143113(105143)Online publication date: Mar-2025
https://doi.org/10.1016/j.micpro.2025.105143
Axinte C(2024)A Methodology for the Synthesis and Evaluation of Hardware AcceleratorsBulletin of the Polytechnic Institute of Iași. Electrical Engineering, Power Engineering, Electronics Section10.2478/bipie-2023-001169:2(91-100)Online publication date: 30-Aug-2024
https://doi.org/10.2478/bipie-2023-0011
Ueno TDel Sozzo ESano K(2024)Flexible Systolic Array Platform on Virtual 2-D Multi-FPGA PlaneProceedings of the International Conference on High Performance Computing in Asia-Pacific Region10.1145/3635035.3637285(84-94)Online publication date: 18-Jan-2024
https://dl.acm.org/doi/10.1145/3635035.3637285
Del Sozzo EConficconi DSano K(2024)Across Time and Space: Senju’s Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/363492017:2(1-33)Online publication date: 30-Apr-2024
https://dl.acm.org/doi/10.1145/3634920
Winandy IDion AGaroche PManni F(2024)A Reactive System-Specific Compilation Chain from Synchronous Dataflow Models to FPGA Netlist2024 IEEE 10th International Conference on Space Mission Challenges for Information Technology (SMC-IT)10.1109/SMC-IT61443.2024.00009(11-21)Online publication date: 15-Jul-2024
https://doi.org/10.1109/SMC-IT61443.2024.00009
Sá Alves GCarlos Bittencourt JDias A(2024)An FPGA Integrated 2D Graphic Processor for Enhanced Digital Design and Computer Architecture EducationIEEE Revista Iberoamericana de Tecnologias del Aprendizaje10.1109/RITA.2024.345885019(176-185)Online publication date: 2024
https://doi.org/10.1109/RITA.2024.3458850
Bertolini RCarloni FConficconi DSantambrogio M(2024)POCA: A PYNQ Offloaded Cryptographic Accelerator on Embedded FPGA-Based Systems2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW63119.2024.00054(194-194)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPSW63119.2024.00054
Venere MGuerrini VBranchini BConficconi DSciuto DSantambrogio M(2024)Towards the Acceleration of the Sparse Blossom Algorithm for Quantum Error Correction2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW63119.2024.00033(106-110)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPSW63119.2024.00033
Valentino FBranchini BConficconi DSciuto DSantambrogio M(2024)An Accurate Union Find Decoder for Quantum Error Correction on the Toric Code2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW63119.2024.00032(99-105)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPSW63119.2024.00032
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