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Bulk JPEG decoding on in-memory processors

Published: 06 June 2022 Publication History

Abstract

JPEG is a common encoding format for digital images. Applications that process large numbers of images can be accelerated by decoding multiple images concurrently. We examine the suitability of using a large array of in-memory processors (PIM) to obtain a high throughput of decoding. The main drawback of PIM processors is that they do not have the same architectural features that are commonly found on CPUs such as floating point, vector units and hardware-managed caches. Despite the lack of features, we demonstrate that it is feasible to build a JPEG decoder for PIM, and evaluate its quality and potential speedup. We show that the quality of decoded images is sufficient for real applications, and there is a significant potential for accelerating image decoding for those applications. We share our experiences in building such a decoder, and the challenges we faced while doing so.

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Cited By

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  • (2024)PhD Forum: Efficient Privacy-Preserving Processing via Memory-Centric Computing2024 43rd International Symposium on Reliable Distributed Systems (SRDS)10.1109/SRDS64841.2024.00039(322-325)Online publication date: 30-Sep-2024
  • (2024)Evaluating the Potential of In-Memory Processing to Accelerate Homomorphic Encryption: Practical Experience Report2024 43rd International Symposium on Reliable Distributed Systems (SRDS)10.1109/SRDS64841.2024.00019(92-103)Online publication date: 30-Sep-2024
  • (2024)PIM-MMU: A Memory Management Unit for Accelerating Data Transfers in Commercial PIM Systems2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00053(627-642)Online publication date: 2-Nov-2024
  • Show More Cited By

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cover image ACM Conferences
SYSTOR '22: Proceedings of the 15th ACM International Conference on Systems and Storage
June 2022
163 pages
ISBN:9781450393805
DOI:10.1145/3534056
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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  • Technion: Israel Institute of Technology
  • USENIX Assoc: USENIX Assoc

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 June 2022

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Author Tags

  1. JPEG
  2. PIM
  3. image processing
  4. in-memory
  5. parallel processing

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SYSTOR '22 Paper Acceptance Rate 12 of 41 submissions, 29%;
Overall Acceptance Rate 108 of 323 submissions, 33%

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Cited By

View all
  • (2024)PhD Forum: Efficient Privacy-Preserving Processing via Memory-Centric Computing2024 43rd International Symposium on Reliable Distributed Systems (SRDS)10.1109/SRDS64841.2024.00039(322-325)Online publication date: 30-Sep-2024
  • (2024)Evaluating the Potential of In-Memory Processing to Accelerate Homomorphic Encryption: Practical Experience Report2024 43rd International Symposium on Reliable Distributed Systems (SRDS)10.1109/SRDS64841.2024.00019(92-103)Online publication date: 30-Sep-2024
  • (2024)PIM-MMU: A Memory Management Unit for Accelerating Data Transfers in Commercial PIM Systems2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00053(627-642)Online publication date: 2-Nov-2024
  • (2024)SwiftRL: Towards Efficient Reinforcement Learning on Real Processing-In-Memory Systems2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS61541.2024.00029(217-229)Online publication date: 5-May-2024
  • (2024)Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00029(263-279)Online publication date: 2-Mar-2024

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